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    USE OF SACRIFICIAL MASKING LAYER AND BACKSIDE EXPOSURE IN FORMING OPENINGS THAT TYPICALLY RECEIVE LIGHT-EMISSIVE MATERIAL, AND ASSOCIATED LIGHT-EMITTING STRUCTURE
    31.
    发明公开
    USE OF SACRIFICIAL MASKING LAYER AND BACKSIDE EXPOSURE IN FORMING OPENINGS THAT TYPICALLY RECEIVE LIGHT-EMISSIVE MATERIAL, AND ASSOCIATED LIGHT-EMITTING STRUCTURE 失效
    VERWENDUNG EINER OPFERMASKIERUNGSSCHICHT UNDRÜCKSEITIGERBELICHTUNG贝德埃尔斯通公司VONLÖCHERNZUR AUFNAHME VON LICHTEMITTIERENDEM材料，ZUGEHÖRIGELICHTEMITTIERENDE STRUKTUR

    公开(公告)号：EP0979525A4

    公开(公告)日：2000-09-27

    申请号：EP98918281

    申请日：1998-04-27

    Applicant: CANDESCENT TECH CORP

    Inventor： HAVEN DUANE A ,  LEARN ARTHUR J ,  PORTER JOHN D

    IPC: G03F7/20 ,  H01J9/227 ,  H01J29/08 ,  H01J29/32 ,  H01J29/87 ,  H01J31/12 ,  H01J29/10

    CPC classification number: H01J29/085 ,  H01J31/127

    Abstract: Openings are created in a structure by a process in which a plate is furnished with a sacrificial patterned masking layer divided into multiple laterally separated mask portions. A primary layer of actinic material is provided over the masking layer and in space between the mask portions. Material of the primary layer not shadowed by a mask formed with the mask portions is backside exposed to actinic radiation. Material of the primary layer not exposed to the radiation is removed. Segments of the masking layer not covered by exposed material of the primary layer are then removed. Consequently, openings extend through the primary layer where the segments of the masking layer have been removed. The process is typically employed in forming an optical device such as a flat-panel cathode-ray tube display in which the openings in the primary layer receive light-emissive material.

    Abstract translation: 通过其中板配备有被分成多个横向分离的掩模部分的牺牲图案化掩模层的工艺在结构中形成开口。 在掩模层上和掩模部分之间的空间中提供光化材料的主要层。 未被由掩模部分形成的掩模遮盖的主要层的材料背面暴露于光化辐射。 未暴露于辐射的主层材料被去除。 然后去除未被主层的暴露材料覆盖的掩蔽层的区段。 因此，开口延伸穿过掩模层的部分已被去除的主层。 该工艺通常用于形成诸如平板阴极射线管显示器的光学装置，其中主层中的开口接收发光材料。

    MULTI-LAYER RESISTOR FOR AN EMITTING DEVICE
    32.
    发明公开
    MULTI-LAYER RESISTOR FOR AN EMITTING DEVICE 失效
    多层阻力发射装置

    公开(公告)号：EP0993679A4

    公开(公告)日：2000-08-30

    申请号：EP98930256

    申请日：1998-06-19

    Applicant: CANDESCENT TECH CORP

    Inventor： KNALL JOHAN N ,  HAVEN DUANE A ,  RAMANI SWAYAMBU

    IPC: H01J9/02 ,  H01J1/304 ,  H01J3/02 ,  H01J29/04 ,  H01J31/12 ,  H01J1/62 ,  H01C7/06 ,  H01J1/30

    CPC classification number: H01J3/022 ,  H01J2201/319 ,  H01J2329/00

    Abstract: An electron-emitting device employs a multi-layer resistor (46). A lower layer (48) of the resistor overlies an emitter electrode (42). An electron-emissive element (54) overlies an upper layer (50) of the resistor. The two resistive layers are of different chemical composition. The upper resistive layer is typically formed with cermet. The lower resistive layer is typically formed with a silicon-carbon compound. In fabricating the device, the upper resistive layer normally serves as an etch stop for protecting the lower resistive layer and the emitter electrode during the etch of an overlying dielectric layer (52) to form an opening (56) in which the electron-emissive element is later provided.

    SPACER LOCATOR DESIGN FOR THREE-DIMENSIONAL FOCUSING STRUCTURES IN A FLAT PANEL DISPLAY
    33.
    发明公开
    SPACER LOCATOR DESIGN FOR THREE-DIMENSIONAL FOCUSING STRUCTURES IN A FLAT PANEL DISPLAY 失效
    ENTWURF EINEM ABSTARDSHALTER-POSITIONSBESTIMMERFÜREINE DREI-DIMENSIONALE FOKUSIERUNGSTRUKTUR IN EINERFLACHANZEIGEGERÄT

    公开(公告)号：EP1019939A4

    公开(公告)日：2000-08-02

    申请号：EP97932501

    申请日：1997-07-16

    Applicant: CANDESCENT TECH CORP

    Inventor： SPINDT CHRISTOPHER J ,  FIELD JOHN E

    IPC: H01J9/24 ,  H01J9/18 ,  H01J29/02 ,  H01J29/87 ,  H01J31/12 ,  H01J19/42

    CPC classification number: H01J29/028 ,  H01J9/185 ,  H01J31/127 ,  H01J2201/025 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8655

    Abstract: A flat panel display (300) having a faceplate structure (320), a backplate structure (330), a focusing structure (333a), and a plurality of spacers (340). The backplate structure includes an electron emitting structure (332) which faces the faceplate structure. The focusing structure has a first surface which is located on the electron emitting structure, and a second surface which extends away from the electron emitting structure. The electrical end of the combination of the focusing structure and the electron emitting structure is located at an imaginary plane located intermediate the first and second surfaces of the focusing structure. The spacers are located between the focusing structure and the light emitting structure. Each spacer is located within a corresponding groove in the focusing structure such that the electrical end of each spacer is located coincident with the electrical end of the combination of the focusing structure and the electron emitting structure.

    Abstract translation: 一种平板显示器，包括：面板结构; 具有电子发射结构的背板结构; 聚焦结构具有耦合到电子发射结构的第一表面和远离电子发射结构延伸的第二表面，聚焦结构和电子发射结构在聚焦结构的第一和第二表面之间具有电端; 位于聚焦结构和面板结构之间的间隔物，间隔物具有位于聚焦结构的电端上方的电端和电子发射结构; 位于所述间隔件的表面的面电极; 以及用于控制面电极的电压以产生邻近面电极的电压分布，该电压分布补偿由位于聚焦结构的电端上方的间隔物的电端引起的电压分布，以及电子发射 结构，所述控制装置包括（a）位于所述间隔件的第一边缘表面处的第一边缘电极，仅沿着所述第一边缘表面的一部分延伸，并且接触所述背板结构和（b）位于第二边缘电极处的​​第二边缘电极 间隔物的边缘表面并接触面板结构。

    A METHOD AND SYSTEM FOR INFRARED DETECTION OF ELECTRICAL SHORT DEFECTS
    34.
    发明公开
    A METHOD AND SYSTEM FOR INFRARED DETECTION OF ELECTRICAL SHORT DEFECTS 审中-公开
    方法和系统红外探测电路短路缺陷

    公开(公告)号：EP1405091A4

    公开(公告)日：2005-07-20

    申请号：EP01990733

    申请日：2001-11-28

    Applicant: CANDESCENT TECH CORP

    Inventor： ENACHESCU MARIUS ,  BELIKOV SERGEY ,  MEIER STEPHEN F

    IPC: G01N25/72 ,  G01M11/00 ,  G01R31/308 ,  G09F9/00 ,  G09G3/00 ,  H01J9/42

    CPC classification number: G09G3/006 ,  G01R31/308

    Abstract: A method and system for detecting electrical short circuit defects in a plate structure of a flat panel display, for example, a field emission display (FED). In one embodiment, the process first applies a stimulation to the electrical conductors of the plate structure. Next, the process creates an infra-red thermal mapping of a cathode region the FED. For example, an infra-red array may be used to snap a picture of the cathode of the FED.Then , the process analyzes the infra-red thermal mapping to determine a region of the FED which contains the electrical short circuit defect. Another embodiment localizes the defect to one sub-pixel by performing an infra-red mapping of the region which the previous IR mapping process determined to contain the electrical short circuit defect. Then, the process analyzes this infra-red mapping to determine a sub-pixel of the FED which contains the electrical short circuit defect.

    UNDERCUTTING TECHNIQUE FOR CREATING COATING IN SPACED-APART SEGMENTS
    35.
    发明公开
    UNDERCUTTING TECHNIQUE FOR CREATING COATING IN SPACED-APART SEGMENTS 有权
    UNTERSCHNEIDUNGSTECHNIK镀在每个远程段的生产

    公开(公告)号：EP1042786A4

    公开(公告)日：2004-09-29

    申请号：EP98955146

    申请日：1998-10-27

    Applicant: CANDESCENT TECH CORP

    Inventor： KNALL JOHAN N

    IPC: H01J9/02 ,  H01L21/00

    CPC classification number: H01J9/025

    Abstract: A technique for creating a patterned coating entails forming a first region (26) over a primary component (22). A second region (28) is formed over part of the first region. The first region is etched so as to undercut the second region, thereby forming a gap (30) below part of the second region. Coating material is then provided over the structure. Due to the presence of the gap, the coating material accumulates over the structure in a pair of segments spaced apart along the gap. One coating segment (32A) overlies the primary component. The other coating segment (32B) overlies the second region.

    A CIRCUIT AND CONTROL METHOD
    39.
    发明公开
    A CIRCUIT AND CONTROL METHOD 审中-公开
    电路和控制方法

    公开(公告)号：EP1018134A4

    公开(公告)日：2001-02-21

    申请号：EP98944670

    申请日：1998-09-02

    Applicant: CANDESCENT TECH CORP

    Inventor： HANSEN RONALD L ,  FRIEDMAN JAY

    IPC: G09G3/20 ,  G09G3/22 ,  H01J31/12 ,  H01J1/30 ,  H01J9/02 ,  H01J23/04 ,  H01J29/28

    CPC classification number: G09G3/2011 ,  G09G3/22 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2320/043 ,  G09G2320/0606 ,  G09G2320/0666

    Abstract: A circuit and method for controlling the color balance of a flat panel display without losing gray scale resolution of the display screen. Within a FED screen (200), a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are activated sequentially by row drivers (220a-220c) and corresponding individual gray scale information (voltages) is driven over the columns by column drivers (240-240c). When the proper voltage is applied across the cathode and anode of the emitters, they release electrons toward a phosphor spot, e.g., red, green, blue, causing an illumination point. Within each column driver (240a-240c), a digital to analog converter (340a-340c) contains two data-in voltage-out transformation functions, a first function corresponding to a first voltage intensity and a second function corresponding to a lesser voltage intensity for a same digital color value.

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