公开(公告)号：US20250151256A1

公开(公告)日：2025-05-08

申请号：US18504426

申请日：2023-11-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H10B12/00 ,  H01L21/768

Abstract: A method includes a number of operations. An oxide layer is formed in an isolation trench over a substrate. A liner is formed over the oxide layer. The liner is oxidized. An implant region is formed over the substrate after the liner is oxidized. The oxide layer and the liner are etched after the implant region is formed. A word line structure is formed over the substrate and across the oxide layer and the liner.

公开(公告)号：US20250151249A1

公开(公告)日：2025-05-08

申请号：US18500681

申请日：2023-11-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Chiang WANG

IPC: H05K9/00

Abstract: An ESD (electrostatic discharge) protection device is disclosed. The ESD protection device is configured to protect an internal circuit. The ESD protection device includes an ESD protection array and a control circuit. The ESD protection array includes several ESD protection units. The control circuit is coupled to the ESD protection array. The control circuit is configured to control a conduction of each of the several ESD protection units so that a determined number of the several ESD protection units are conducted.

公开(公告)号：US12293982B2

公开(公告)日：2025-05-06

申请号：US17839806

申请日：2022-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo

IPC: H01L23/00

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a first semiconductor substrate, a first conductive pad, and a first hybrid bonding pad. The first conductive pad is over the first semiconductor substrate. The first hybrid bonding pad is on the first conductive pad. The first hybrid bonding pad includes nano-twins copper. A thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

公开(公告)号：US20250141449A1

公开(公告)日：2025-05-01

申请号：US18493817

申请日：2023-10-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chang-Ting Wu

IPC: H03K19/017

Abstract: An off-chip driver (OCD), a pull-up driver of the OCD and the pull-down driver of the OCD are provided. The pull-up driver includes a main current source circuit and a main base circuit. The main current source circuit is connected between a connecting pad and a high reference voltage. The main current source circuit provides a main current value in response to a main control signal. The matching resistance value is associated with the main current value. The main base circuit is connected to the main current source circuit in parallel, and determines a base value of the matching resistance value.

公开(公告)号：US20250140651A1

公开(公告)日：2025-05-01

申请号：US18520955

申请日：2023-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PING HSU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

公开(公告)号：US20250132194A1

公开(公告)日：2025-04-24

申请号：US18520114

申请日：2023-11-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JAR-MING HO

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

公开(公告)号：US12283518B2

公开(公告)日：2025-04-22

申请号：US17824481

申请日：2022-05-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chih-Hsuan Yeh

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate, wherein the translucent layer includes a mask opening of contact portion which exposes a portion of the mask substrate; providing a stack structure including an etch stop layer on a bottom conductive layer and a first inter-dielectric layer on the etch stop layer, and forming a pre-process mask layer on the stack structure; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a region of body portion corresponding to the translucent layer, and a hole of contact portion corresponding to the mask opening of contact portion.

公开(公告)号：US20250126873A1

公开(公告)日：2025-04-17

申请号：US18991791

申请日：2024-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JHEN-YU TSAI

IPC: H10D64/27 ,  H10D62/10 ,  H10D64/01

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode.

公开(公告)号：US20250125257A1

公开(公告)日：2025-04-17

申请号：US18991798

申请日：2024-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L23/528 ,  H10D62/13 ,  H10D64/23 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: The present disclosure provides a method of manufacturing semiconductor structure. The method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.

公开(公告)号：US20250125190A1

公开(公告)日：2025-04-17

申请号：US18380312

申请日：2023-10-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/16

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.