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公开(公告)号：KR101902402B1
公开(公告)日：2018-09-28
申请号：KR1020120035558
申请日：2012-04-05
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/28
CPC classification number: H01L21/308 , H01L21/0337 , H01L21/31144 , H01L21/76802 , H01L21/76816 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10888
Abstract: 미세패턴형성방법및 이를이용한반도체장치의제조방법이제공된다. 상기미세패턴형성방법은기판상에피식각막을형성하고, 상기피식각막상에제1 마스크패턴을형성하고, 상기제1 마스크패턴에이온주입을하여제2 마스크패턴을형성하고, 상기제2 마스크패턴을이용하여상기피식각막을식각하는것을포함한다.
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公开(公告)号：KR1020130007885A
公开(公告)日：2013-01-21
申请号：KR1020110068507
申请日：2011-07-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/306 , H01L21/31053 , H01L21/31111 , H01L22/12 , H01L22/26 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L27/0688 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a 3d semiconductor device is provided to facilitate a planarization process by performing an anisotropic etching on a part of a lamination film structure. CONSTITUTION: A cell array region(A) and a peripheral circuit region(C) are formed in a substrate. A peripheral structure is formed on the substrate. The peripheral structure includes peripheral circuits. The substrate is recessed in the cell array region. A recess part has a bottom surface.
Abstract translation: 目的：提供一种用于制造3d半导体器件的方法，以通过对层压膜结构的一部分进行各向异性蚀刻来促进平坦化处理。 构成：在衬底中形成电池阵列区域（A）和外围电路区域（C）。 在基板上形成周边结构。 外设结构包括外围电路。 衬底凹入电池阵列区域。 凹部具有底面。
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公开(公告)号：KR1020120064820A
公开(公告)日：2012-06-20
申请号：KR1020100126029
申请日：2010-12-10
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/28273 , H01L21/31051 , H01L21/67063 , H01L21/76256
Abstract: PURPOSE: A method of manufacturing a semiconductor device is provided to prevent dishing by forming an inter-layer insulating film having a flat upper side for each area on a substrate. CONSTITUTION: A second barrier film is formed on a first interlayer insulating film. A second secondary inter-layer insulating film is formed by etching a part of the first interlayer insulating film and the second barrier film. A part of the second barrier film and the second secondary inter-layer insulating film is primarily ground. The second secondary inter-layer insulating film is secondarily ground in order to expose a first barrier layer pattern and the second barrier film. A second barrier film pattern(20b) and a second inter-layer insulating film(18b) are formed on a substrate in a second region.
Abstract translation: 目的：提供一种制造半导体器件的方法，用于通过为基板上的每个区域形成具有平坦的上侧的层间绝缘膜来防止凹陷。 构成：在第一层间绝缘膜上形成第二阻挡膜。 通过蚀刻第一层间绝缘膜和第二阻挡膜的一部分来形成第二次级层间绝缘膜。 主要研磨第二阻挡膜和第二次级层间绝缘膜的一部分。 第二次级层间绝缘膜被二次接地以暴露第一阻挡层图案和第二阻挡膜。 在第二区域中的基板上形成第二阻挡膜图案（20b）和第二层间绝缘膜（18b）。
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公开(公告)号：KR1020120047325A
公开(公告)日：2012-05-11
申请号：KR1020100107827
申请日：2010-11-01
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/28 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/0688
Abstract: PURPOSE: A three-dimensional semiconductor device for improving the degree of integration is provided to prevent other structures from being damaged while a cell structure is pattered since a top portion of the cell structure is formed by patterning an upper thin film structure. CONSTITUTION: Provided is a substrate(10) including a cell array region(CAR) and a peripheral circuit region(PERI). A peripheral structure(100) including peripheral circuits is formed on the substrate in the peripheral circuit region. A lower cell structure(205) is formed on the substrate in the cell array region. An insulating layer(110) covering the peripheral structure and the lower cell structure are formed on the substrate. The insulating layer is planarized by using upper sides of the lower cell structure and the peripheral structure as a planarization end point. A top cell structure is formed on the lower cell structure.
Abstract translation: 目的：提供一种用于提高集成度的三维半导体器件，以防止其他结构在单元结构被图案化时被损坏，因为通过图案化上部薄膜结构形成单元结构的顶部。 构成：提供了包括电池阵列区域（CAR）和外围电路区域（PERI）的基板（10）。 在外围电路区域中的基板上形成包括外围电路的外围结构（100）。 下电池结构（205）形成在电池阵列区域中的衬底上。 在基板上形成覆盖周边结构和下部单元结构的绝缘层（110）。 通过使用下单元结构的上侧和外围结构作为平坦化终点，将绝缘层平坦化。 顶部单元结构形成在下单元结构上。
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公开(公告)号：KR1020100061034A
公开(公告)日：2010-06-07
申请号：KR1020080119907
申请日：2008-11-28
Applicant: 삼성전자주식회사
IPC: H01L21/308 , H01L21/027
CPC classification number: H01L21/0337 , H01L21/0338
Abstract: PURPOSE: A fabricating method of semiconductor integrated circuit devices are provided to form a spacer layer on a hard mask pattern with conformal by forming a line spacer with a low temperature oxide film. CONSTITUTION: A hard mask layer is formed on a semiconductor substrate(100). A first etching mask including a plurality of first line patterns is formed on the hard mask layer. The hard mask layer is etched and the first hard mask pattern is formed. A second etching mask including a plurality of second line patterns is formed in the first hard mask pattern. The first hard mask pattern is etched to form the second hard mask pattern(122). The spacer(131) is formed in the sidewall of the second hard mask pattern.
Abstract translation: 目的：提供半导体集成电路器件的制造方法，通过形成具有低温氧化膜的线间隔物，在硬掩模图案上形成间隔层。 构成：在半导体衬底（100）上形成硬掩模层。 在硬掩模层上形成包括多个第一线图案的第一蚀刻掩模。 蚀刻硬掩模层并形成第一硬掩模图案。 在第一硬掩模图案中形成包括多个第二线图案的第二蚀刻掩模。 蚀刻第一硬掩模图案以形成第二硬掩模图案（122）。 间隔物（131）形成在第二硬掩模图案的侧壁中。
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Patent Agency Ranking
公开(公告)号：KR101970941B1
公开(公告)日：2019-08-13
申请号：KR1020120090784
申请日：2012-08-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
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公开(公告)号：KR1020170053435A
公开(公告)日：2017-05-16
申请号：KR1020150155950
申请日：2015-11-06
Applicant: 삼성전자주식회사
CPC classification number: H04N5/23293 , G06T11/001 , G06T11/60 , H04N1/00411 , H04N1/00453 , H04N2201/0084 , H04N2201/0096 , H04N2201/0098
Abstract: 본발명의다양한실시예들은, 전자장치에있어서, 상기전자장치의화면상에서표시되는이미지편집도구에포함되는복수의색 할당영역들에대한정보를저장하는저장부; 상기전자장치의화면상에서복수의색 할당영역들을포함하는이미지편집도구를표시하는표시부; 및색 추출과관련된입력에대응하여, 상기전자장치에설치된미리설정된애플리케이션을실행하고, 상기애플리케이션의실행화면의적어도일부영역에서선택된색을상기이미지편집도구의색 할당영역에표시하도록제어하는제어부;를포함할수 있다. 또한, 본발명의다양한실시예들은다른실시예들이가능할수 있다.
Abstract translation: 本发明的各种实施例中，在电子设备中，包括：存储单元，用于存储信息的多种颜色包括在电子设备的屏幕上显示的图像编辑工具分配的区域; 显示单元，在电子设备的屏幕上显示包括多个颜色分配区域的图像编辑工具; 对应于与mitsaek提取的输入端，用于执行安装在电子装置中的预定的应用控制单元，控制成显示至少在应用到分配给图像编辑工具的区域中的颜色的执行屏幕的部分区域中选择的颜色;所述 你可以包括它。 另外，在其他实施例中，本发明的各种实施例也是可能的。
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公开(公告)号：KR1020150029873A
公开(公告)日：2015-03-19
申请号：KR1020130108819
申请日：2013-09-11
Applicant: 삼성전자주식회사
Inventor： 김효정
IPC: D06F33/02
CPC classification number: D06F33/02 , D06F35/006 , D06F39/04 , D06F39/045 , D06F2202/04 , D06F2202/085 , D06F2204/04 , D06F2204/084 , D06F2204/086
Abstract: 세탁 효과를 높이기 위해 물을 가열하여 세탁을 진행하는 삶는 세탁 코스 기능을 가지는 세탁기 및 그 제어방법을 제안한다.
초기 급수된 물의 온도에 따라 정해진 시간 동안 물을 가열하고, 가열된 물의 온도가 설정 온도보다 낮은 경우에는 물을 배수하고, 물의 온도가 설정 온도 이상인 경우에는 물을 배수하지 않고 초기 급수 수량을 유지함으로써 세탁 효과를 높일 수 있다. 또한, 초기 급수된 수량을 유지한 상태로 정해진 세탁 시간에 고온의 목표 온도에 도달하도록 함으로써 세탁 온도에 의한 세탁 효과를 유지할 수 있게 된다.Abstract translation: 本发明涉及一种洗衣机，其具有为了提高洗涤效果而加热水进行洗涤的沸腾洗涤功能及其控制方法。 本发明可以根据首先供给的水的温度加热水来提高洗涤效果，当加热的水的温度低于预设温度时排出水，并且保持初始供水量而没有 当水温等于或大于预设温度时排水。 此外，本发明可以在保持初始供给水量的状态下，通过使洗涤温度在确定的洗涤时间达到高目标温度，根据洗涤温度来提供洗涤效果。
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公开(公告)号：KR1020140118132A
公开(公告)日：2014-10-08
申请号：KR1020130033514
申请日：2013-03-28
Applicant: 삼성전자주식회사
IPC: D06F33/02
CPC classification number: D06F33/02 , D06F37/24 , D06F37/304 , D06F37/40 , D06F39/003 , Y02B40/50
Abstract: Provided are a washing machine capable of performing an optimal process by detecting overload conditions of a motor, and a method for controlling the same. The washing machine detects overload conditions of a motor by measuring speed and current of the motor through the left and right stirring of the motor before water supply is being done after the laundry is input, and changes RPM and operation rate of washing process, rinsing process, and spin-dry process upon overload conditions to protect the motor while performing an optimal washing process.
Abstract translation: 提供一种能够通过检测电动机的过载状况来进行最佳处理的洗衣机及其控制方法。 洗衣机通过在输入衣物之后进行供水之前通过电动机的左右搅拌测量电动机的速度和电流来检测电动机的过载状况，并且改变RPM和洗涤过程的操作速率，漂洗过程 ，并在过载条件下进行旋转干燥处理，以在执行最佳洗涤过程时保护电机。
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公开(公告)号：KR1020130113180A
公开(公告)日：2013-10-15
申请号：KR1020120035558
申请日：2012-04-05
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/28
CPC classification number: H01L21/308 , H01L21/0337 , H01L21/31144 , H01L21/76802 , H01L21/76816 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L21/0279 , H01L21/76838 , H01L21/76895
Abstract: PURPOSE: A method for forming a fine pattern of a semiconductor device and a method for manufacturing the semiconductor device using the same are provided to easily form the fine pattern by using a second mask pattern. CONSTITUTION: An etching target layer (210) is formed on a substrate. A first mask pattern is formed on the etching target layer. A second mask pattern (221) is formed by injecting ions into the first mask pattern. The etching target layer is etched by using the second mask pattern.
Abstract translation: 目的：提供一种用于形成半导体器件的精细图案的方法和使用其制造半导体器件的方法，以通过使用第二掩模图案容易地形成精细图案。 构成：在基板上形成蚀刻目标层（210）。 在蚀刻目标层上形成第一掩模图案。 通过将离子注入到第一掩模图案中形成第二掩模图案（221）。 通过使用第二掩模图案蚀刻蚀刻目标层。
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