公开(公告)号：KR1020130113180A

公开(公告)日：2013-10-15

申请号：KR1020120035558

申请日：2012-04-05

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  김봉현 ,  김수민 ,  김효정 ,  박창민 ,  홍수진

IPC: H01L21/027 ,  H01L21/28

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L21/0279 ,  H01L21/76838 ,  H01L21/76895

Abstract: PURPOSE: A method for forming a fine pattern of a semiconductor device and a method for manufacturing the semiconductor device using the same are provided to easily form the fine pattern by using a second mask pattern. CONSTITUTION: An etching target layer (210) is formed on a substrate. A first mask pattern is formed on the etching target layer. A second mask pattern (221) is formed by injecting ions into the first mask pattern. The etching target layer is etched by using the second mask pattern.

Abstract translation: 目的：提供一种用于形成半导体器件的精细图案的方法和使用其制造半导体器件的方法，以通过使用第二掩模图案容易地形成精细图案。 构成：在基板上形成蚀刻目标层（210）。 在蚀刻目标层上形成第一掩模图案。 通过将离子注入到第一掩模图案中形成第二掩模图案（221）。 通过使用第二掩模图案蚀刻蚀刻目标层。

公开(公告)号：KR1020100054004A

公开(公告)日：2010-05-24

申请号：KR1020080112916

申请日：2008-11-13

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  박영근 ,  양준규 ,  최시영 ,  황기현 ,  안재영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28282 ,  H01L21/28141 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66833 ,  H01L29/792

Abstract: PURPOSE: A nonvolatile memory device is provided to improve the retention and reliability by minimizing the change of the threshold voltage of a memory cell of the non-volatile memory device even if a program and erase are repeated. CONSTITUTION: In a nonvolatile memory device, a turner insulating layer is formed on a semiconductor substrate. A charge trapping layer(120) is formed on the turner insulating layer. A blocking insulation film(130) is formed on the charge trapping layer. A gate structure(150) is formed on a blocking insulation film. The charge spreading blockade are respectively is adjacent to the both walls of the gate structure.

Abstract translation: 目的：提供非易失性存储器件，用于通过最小化非易失性存储器件的存储单元的阈值电压的变化来改善保持和可靠性，即使重复编程和擦除。 构成：在非易失性存储器件中，在半导体衬底上形成转子绝缘层。 电荷捕获层（120）形成在转子绝缘层上。 在电荷俘获层上形成阻挡绝缘膜（130）。 栅极结构（150）形成在阻挡绝缘膜上。 电荷扩散阻挡分别与栅极结构的两个壁相邻。

公开(公告)号：KR1020090128885A

公开(公告)日：2009-12-16

申请号：KR1020080054860

申请日：2008-06-11

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  홍수진 ,  연국현 ,  최시영 ,  이선길

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/823878 ,  H01L27/10894 ,  H01L27/11546

Abstract: PURPOSE: A method for forming an isolation film without a liner nitride film on a PMOS region is provided to obtain an current gain on a cell region, an NMOS region and a PMOS region through optimum assembly of stress, by using the liner nitride and a material of the isolation film filling a trench. CONSTITUTION: A mask pattern is formed on a semiconductor substrate(100). A trench is formed on a cell region, a PMOs region and an NMOS region by etching the semiconductor substrate. A side wall oxide(122) and a protective film are formed on the trench in sequence. The protective film is removed from the PMOS region. The trench of the semiconductor substrate is buried as a first isolation insulating layer(142). The first isolation insulating layer is removed from the trench of the NMOS region and the cell region. A liner silicon nitride(126) is formed on the front of the semiconductor substrate. The trench of the cell region and the NMOs region of the semiconductor substrate is buried as a second isolation insulating film.

Abstract translation: 目的：提供一种在PMOS区上形成不含衬垫氮化物膜的隔离膜的方法，通过使用衬里氮化物和通过使用衬垫氮化物来获得电池区域，NMOS区域和PMOS区域上的电流增益，通过最佳的应力组装 隔离膜的材料填充沟槽。 构成：在半导体衬底（100）上形成掩模图案。 通过蚀刻半导体衬底，在单元区域，PMO区域和NMOS区域上形成沟槽。 依次在沟槽上形成侧壁氧化物（122）和保护膜。 从PMOS区域去除保护膜。 半导体衬底的沟槽被掩埋为第一隔离绝缘层（142）。 从NMOS区域和单元区域的沟槽去除第一隔离绝缘层。 衬底氮化硅（126）形成在半导体衬底的前面。 单元区域的沟槽和半导体衬底的NMO区域被掩埋为第二隔离绝缘膜。

公开(公告)号：KR1020130077213A

公开(公告)日：2013-07-09

申请号：KR1020110145800

申请日：2011-12-29

Applicant: 삼성전자주식회사

Inventor： 유종렬 ,  정성훈 ,  김봉현 ,  김효정 ,  신동운 ,  홍수진

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02381 ,  H01L21/26513 ,  H01L21/823842 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66712 ,  H01L29/7802

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce the surface resistance of an NMOS electrode by preventing the loss of an n-type impurity. CONSTITUTION: A first mask (106) covering a polysilicon layer corresponding to a second region is formed. An N-region (110) is formed by injecting an n-type impurity to a polysilicon layer corresponding to a first region. Nitrogen is injected into the N-region. A second mask covering the N-region is formed. A P-region is formed by injecting a p-type impurity to the polysilicon layer corresponding to the second region. [Reference numerals] (AA) Nitrogen; (BB) First region; (CC) Second region

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过防止n型杂质的损失来降低NMOS电极的表面电阻。 构成：形成覆盖对应于第二区域的多晶硅层的第一掩模（106）。 通过向对应于第一区域的多晶硅层注入n型杂质形成N区（110）。 氮注入N区。 形成覆盖N区的第二掩模。 通过向对应于第二区域的多晶硅层注入p型杂质形成P区。 （标号）（AA）氮气; （BB）第一区; （CC）第二地区

公开(公告)号：KR1020100104725A

公开(公告)日：2010-09-29

申请号：KR1020090023338

申请日：2009-03-19

Applicant: 삼성전자주식회사

Inventor： 박영근 ,  안재영 ,  양준규 ,  신동운

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L21/28141 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76224

Abstract: PURPOSE: It forms into the charge differential shift pattern having the profile which the manufacturing method of the charge trap type memory device perpendiculars a part of the charge trapping layer on the element isolation film. CONSTITUTION: A tunnel oxide film(110) is formed on the substrate(100). The charge trapping layer(120) is formed on the turner insulating layer. The blocking film(130) is formed on the charge trapping layer. The gate electrode(142) separating with the trench is formed on the blocking film. It is formed into the charge differential shift pattern having the profile in which a part of the charge trapping layer corresponding to the trench perpendiculars.

Abstract translation: 目的：形成具有电荷陷阱型存储装置的制造方法垂直于元件隔离膜上的电荷俘获层的一部分的形状的电荷差分移位图形。 构成：在衬底（100）上形成隧道氧化膜（110）。 电荷捕获层（120）形成在转子绝缘层上。 阻挡膜（130）形成在电荷俘获层上。 在阻挡膜上形成与沟槽分离的栅电极（142）。 其形成为电荷差分移位图案，其具有其中对应于沟槽的电荷捕获层的一部分垂直的轮廓。

公开(公告)号：KR1020100093349A

公开(公告)日：2010-08-25

申请号：KR1020090012496

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 안재영 ,  황기현 ,  박영근 ,  양준규 ,  주병선 ,  신동운

IPC: H01L21/205 ,  C23C16/44

CPC classification number: H01L21/76837 ,  C23C16/045 ,  C23C16/45542 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228

Abstract: PURPOSE: A method for forming a vapor thin film and a method for manufacturing a semiconductor integrated circuit device are provided to efficiently fill a space between fine patterns by preventing a void inside the thin film. CONSTITUTION: A substrate is loaded inside a chamber of an atomic layer deposition device(S110). A source gas is supplied to a chamber(S120). A source gas which is not reacted with the substrate or absorbed in the substrate is purged(S130). An electric field is vertically formed to the substrate by applying a bias to the substrate(S140). The reaction gas is supplied to the chamber(S150). An oxidation reaction gas which is not reacted is purged(S160).

Abstract translation: 目的：提供一种形成蒸气薄膜的方法和半导体集成电路器件的制造方法，以通过防止薄膜内部的空隙来有效地填充精细图案之间的空间。 构成：将基板装载在原子层沉积装置的室内（S110）。 源气体被供给到室（S120）。 清除未与基板反应或吸收在基板中的源气体（S130）。 通过向衬底施加偏压来垂直形成电场到衬底（S140）。 将反应气体供给到室（S150）。 清除未反应的氧化反应气体（S160）。

公开(公告)号：KR1020090087643A

公开(公告)日：2009-08-18

申请号：KR1020080013008

申请日：2008-02-13

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  박태서 ,  최시영 ,  홍수진 ,  김미진

IPC: H01L21/76 ,  H01L21/265

CPC classification number: H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

Abstract: A method of manufacturing the semiconductor device is provided to reduce the deterioration of device by the high temperature process by forming the oxynitride film in the low-temperature process. Third peripheral region trenches(110a, 110b, 110c) through the first and cell region trench(210) are formed on the peripheral region(100) and cell region(200) of the substrate(10). Oxide films(120, 220) are formed on the surface of third peripheral region trenches through the first and cell region trenches. The oxide film is formed by the thermal oxidation method, and the rapid thermal oxidation or the chemical vapor deposition. Filling isolation layers(160, 260) are planarized by the chemical mechanical polishing or the etch back.

Abstract translation: 提供一种制造半导体器件的方法，以通过在低温工艺中形成氧氮化物膜来减少由高温工艺引起的器件劣化。 通过第一和单元区域沟槽（210）的第三外围区域沟槽（110a，110b，110c）形成在衬底（10）的外围区域（100）和单元区域（200）上。 氧化膜（120,220）通过第一和单元区域沟槽形成在第三外围区域沟槽的表面上。 氧化膜通过热氧化法形成，并且快速热氧化或化学气相沉积。 填充隔离层（160,260）通过化学机械抛光或回蚀刻而平坦化。

公开(公告)号：KR102106885B1

公开(公告)日：2020-05-06

申请号：KR1020130028102

申请日：2013-03-15

Applicant: 삼성전자주식회사

Inventor： 임한진 ,  김봉현 ,  남석우 ,  신동운 ,  전인상 ,  홍수진

IPC: C23C16/22 ,  C23C16/44 ,  H01L21/205

公开(公告)号：KR101902402B1

公开(公告)日：2018-09-28

申请号：KR1020120035558

申请日：2012-04-05

Applicant: 삼성전자주식회사

Inventor： 신동운 ,  김봉현 ,  김수민 ,  김효정 ,  박창민 ,  홍수진

IPC: H01L21/027 ,  H01L21/28

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: 미세패턴형성방법및 이를이용한반도체장치의제조방법이제공된다. 상기미세패턴형성방법은기판상에피식각막을형성하고, 상기피식각막상에제1 마스크패턴을형성하고, 상기제1 마스크패턴에이온주입을하여제2 마스크패턴을형성하고, 상기제2 마스크패턴을이용하여상기피식각막을식각하는것을포함한다.

公开(公告)号：KR1020110021238A

公开(公告)日：2011-03-04

申请号：KR1020090078906

申请日：2009-08-25

Applicant: 삼성전자주식회사

Inventor： 양준규 ,  안재영 ,  박영근 ,  황기현 ,  신동운 ,  이주열

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/513 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L21/02362

Abstract: PURPOSE: A non-volatile memory and a forming method thereof are provided to improve the retention property of a device by alleviating the electrical field applied to the edge of the active area by comprising a barrier capping layer. CONSTITUTION: A semiconductor substrate(100) including an element separation layer(105) is prepared for defining the active area. A tunnel insulating layer(110) is formed on the semiconductor substrate of the active area. A charge trapping layer(120) is formed on the tunnel insulating layer. A blocking insulation film(140) is formed on the charge trapping layer and the element isolation film.

Abstract translation: 目的：提供一种非易失性存储器及其形成方法，以通过包括阻挡覆盖层减轻施加到有源区域的边缘的电场来改善器件的保持性。 构成：准备包括元件分离层（105）的半导体衬底（100）以限定有效面积。 隧道绝缘层（110）形成在有源区的半导体衬底上。 电荷俘获层（120）形成在隧道绝缘层上。 在电荷捕获层和元件隔离膜上形成阻挡绝缘膜（140）。