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公开(公告)号：KR1020130007885A
公开(公告)日：2013-01-21
申请号：KR1020110068507
申请日：2011-07-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/306 , H01L21/31053 , H01L21/31111 , H01L22/12 , H01L22/26 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L27/0688 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a 3d semiconductor device is provided to facilitate a planarization process by performing an anisotropic etching on a part of a lamination film structure. CONSTITUTION: A cell array region(A) and a peripheral circuit region(C) are formed in a substrate. A peripheral structure is formed on the substrate. The peripheral structure includes peripheral circuits. The substrate is recessed in the cell array region. A recess part has a bottom surface.
Abstract translation: 目的：提供一种用于制造3d半导体器件的方法，以通过对层压膜结构的一部分进行各向异性蚀刻来促进平坦化处理。 构成：在衬底中形成电池阵列区域（A）和外围电路区域（C）。 在基板上形成周边结构。 外设结构包括外围电路。 衬底凹入电池阵列区域。 凹部具有底面。
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公开(公告)号：KR100442863B1
公开(公告)日：2004-08-02
申请号：KR1020010046517
申请日：2001-08-01
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L28/55 , H01L21/76807 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
Abstract: 금속-절연체-금속 커패시터 및 다마신 배선 구조를 갖는 반도체 소자의 제조 방법을 개시한다. 본 발명에 따른 반도체 소자의 제조 방법에서는, 반도체 기판 상의 하부 절연막 내에 하부 절연막과 단차가 없게 제1 금속 배선 및 제2 금속 배선을 형성한다. 제1 금속 배선 및 제2 금속 배선이 형성된 결과물 상에 제2 금속 배선의 상면을 노출시키는 홀 영역을 갖는 제1 절연막과 제2 절연막을 순차적으로 형성한다. 홀 영역의 내벽과 바닥에 유전막을 개재시켜 제2 절연막의 상면과 단차가 없게 홀 영역을 완전히 매립하는 커패시터 상부전극을 형성한다. 상부전극이 형성된 결과물 상에 제3 절연막 및 제4 절연막을 형성한다. 제4, 제3, 제2 및 제1 절연막을 관통하여 제1 금속 배선의 상면에 접하는 다마신 배선 구조와, 제4 및 제3 절연막을 관통하여 상부전극의 상면에 접하는 콘택 플러그를 형성한다.
Abstract translation: 一种用于制造具有金属 - 绝缘体 - 金属（MIM）电容器和镶嵌布线层结构的半导体器件的方法，其中第一和第二金属布线层形成在半导体衬底上的下介电层中，使得第一和第二金属布线层的顶表面 并且第二金属布线层和下介电层是平坦的。 第一和第二介电层依次形成为具有暴露第二金属布线层的顶表面的孔。 电容器的上电极形成在孔区中，使得上电极和第二电介质层的顶表面处于水平。 在衬底上顺序形成第三和第四介电层。 镶嵌结构形成为与第一金属布线层的顶表面接触，并且形成接触插塞以接触上电极的顶表面。
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公开(公告)号：KR1020000026663A
公开(公告)日：2000-05-15
申请号：KR1019980044303
申请日：1998-10-22
Applicant: 삼성전자주식회사
Inventor： 한자형
IPC: H01L21/304
Abstract: PURPOSE: A device for chemical mechanical polishing is provided to prevent the edge part of the wafer from being severely polished by cutting out the edge part of the carrier film which acts as a medium or forming the carrier part with a different material from the original one. CONSTITUTION: A device comprises a polishing pad(100), a wafer(102), a carrier film(104), and a carrier(106). The wafer is adhered to the carrier. The carrier film is installed between the carrier and the wafer and transmits the down force from the carrier to the wafer(102). The polishing pad polishes the wafer. The edge of the carrier film is cut out in order to prevent the edge part from being severely polished.
Abstract translation: 目的：提供一种用于化学机械抛光的装置，以通过切除作为介质的载体膜的边缘部分或形成载体部分的材料与原来的不同材料来防止晶片的边缘部分被严重抛光 。 构成：装置包括抛光垫（100），晶片（102），载体膜（104）和载体（106）。 晶片粘附到载体上。 载体膜安装在载体和晶片之间，并将载体的向下力传递到晶片（102）。 抛光垫抛光晶片。 切除载体膜的边缘以防止边缘部分被严重抛光。
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公开(公告)号：KR101807250B1
公开(公告)日：2017-12-11
申请号：KR1020110068507
申请日：2011-07-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/306 , H01L21/31053 , H01L21/31111 , H01L22/12 , H01L22/26 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
Abstract: 3차원반도체장치의제조방법이제공된다. 3차원반도체장치의제조방법은셀 어레이영역및 주변회로영역을포함하는기판을준비하는것; 주변회로영역의기판상에, 주변회로들을포함하는주변구조체를형성하는것; 셀어레이영역의기판을리세스시켜, 주변구조체의상부면보다아래에바닥면을갖는오목부를형성하는것; 오목부가형성된기판을컨포말하게덮으며, 연속적으로적층된복수의박막들을포함하는적층막구조체를형성하되, 적층막구조체는셀 어레이영역상에서최저상면을갖고, 주변회로영역상에서최고상면을갖는것; 적층막구조체를컨포말하게덮는평탄화정지막을형성하는것; 및셀 어레이영역상의평탄화정지막을평탄화종료점으로이용하여적층막구조체를평탄화함으로써, 셀어레이영역과주변회로영역사이에서박막들의상부면들과주변구조체의상부면을동시에노출시키는것을포함한다.
Abstract translation: 提供了一种制造三维半导体器件的方法。 一种制造三维半导体器件的方法包括：准备包括单元阵列区域和外围电路区域的衬底; 在外围电路区域中在衬底上形成包括外围电路的外围结构; 凹进单元阵列区域的衬底以形成凹槽，凹槽具有在外围结构的顶表面下方的底表面; 的凹部被形成为覆盖该衬底共形，以形成层压薄膜结构，其包括多个薄膜依次层叠，在具有最小的顶面，上单元阵列区域的外围电路区域，其具有顶上表面上的层压薄膜结构 。 形成共形地覆盖层压膜结构的平坦停止膜; 通过使用层叠在膜结构的平坦化终点膜，包括那些在单元阵列区和外围电路区之间的同时暴露薄膜结构的衣服的上表面和外周面平坦化mitsel阵列区域平坦化终止。
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公开(公告)号：KR1020080072375A
公开(公告)日：2008-08-06
申请号：KR1020070011064
申请日：2007-02-02
Applicant: 삼성전자주식회사
Inventor： 한자형
IPC: H01L21/304
Abstract: A polishing pad of a chemical mechanical polishing apparatus and a manufacturing method thereof are provided to effectively increase a polishing speed by increasing a surface energy without decreasing a flatness of a polyurethane material. A polyurethane material and hetero-particle(120) are added in a mixing drum and the hetero-particles are mixed with the polyurethane material. The polyurethane material and the hetero-particles are stirred. The polyurethane material and the hetero-particles are cured to form an ingot of a polishing pad(100) of a CVD(Chemical Vapor Deposition) apparatus. A surface energy of the polyurethane material is increased by mixing the hetero-particles with the polyurethane material. The hetero-particle is selected from the group consisting of gold, platinum, silver, and copper.
Abstract translation: 提供化学机械抛光装置的抛光垫及其制造方法，以通过增加表面能而不降低聚氨酯材料的平整度来有效地提高抛光速度。 将聚氨酯材料和异质颗粒（120）加入到混合鼓中，并将异质颗粒与聚氨酯材料混合。 搅拌聚氨酯材料和异质颗粒。 固化聚氨酯材料和异质颗粒以形成CVD（化学气相沉积）设备的抛光垫（100）的锭。 通过将异质颗粒与聚氨酯材料混合来增加聚氨酯材料的表面能。 异质粒子选自金，铂，银和铜。
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Patent Agency Ranking
公开(公告)号：KR100510453B1
公开(公告)日：2005-10-21
申请号：KR1019980002778
申请日：1998-02-02
Applicant: 삼성전자주식회사
Inventor： 한자형
IPC: H01L21/304
Abstract: 화학 기계적 연마 공정에 이용되는 캐리어 필름을 마운팅하는 방법과 캐리어 필름 마운팅 플레이트에 관하여 개시한다. 전자는 마운팅된 캐리어 필름의 마운팅 온도를 국부적으로 조절하여 마운팅된 캐리어 필름의 두께를 국부적으로 조절하는 것을 특징으로 한다. 후자는 그 상부에 장착되는 웨이퍼에 대한 화학 기계적 연마율에 따라 동심원 형태로 구비된 단열막과, 단열막에 의하여 영역 구분된 각각의 영역에 구비된 도우넛 형태의 발열 수단 및 발열 수단에 연결된 온도 조절기를 포함하여 구비하여 마운팅된 캐리어 필름의 마운팅 온도를 조절하여 마운팅된 캐리어 필름의 두께를 조절하는 것을 특징으로 한다. 이로써, 캐리어 필름의 두께와 밀접한 관련을 갖는 연마율을 동일 웨이퍼 상에서 국부적으로 조절할 수 있다.
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公开(公告)号：KR1020020052646A
公开(公告)日：2002-07-04
申请号：KR1020000082057
申请日：2000-12-26
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L29/788
CPC classification number: H01L27/11521 , H01L27/115 , H01L27/11524
Abstract: PURPOSE: A method for fabricating a non-volatile memory device is provided to simplify a fabricating process, reduce thickness of interlayer dielectric, and improve a speed characteristic of a semiconductor device. CONSTITUTION: A gate pattern(120) is formed on a semiconductor substrate(100). A polishing stopper(114) is formed on the semiconductor substrate(100) including the gate pattern(120) by using a blanket method. A multi-layer including an interlayer dielectric(116) is deposited on the gate pattern(120). The interlayer dielectric(116), the polishing stopper(114), and a gate oxide layer of a common source line formation region are etched partially by performing a photo-lithography process and an etch process. A conductive material is deposited thereon. A planarization process is performed by a chemical mechanical polishing process. A polysilicon layer for control gate is exposed by performing an etch back process. A silicide layer(118A) is formed on the gate pattern(120) and the common source line.
Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，以简化制造工艺，减小层间电介质的厚度，并提高半导体器件的速度特性。 构成：在半导体衬底（100）上形成栅极图案（120）。 通过使用毯式方法在包括栅极图案（120）的半导体衬底（100）上形成抛光停止器（114）。 包括层间电介质（116）的多层沉积在栅极图案（120）上。 通过进行光刻工艺和蚀刻工艺，部分地蚀刻层间电介质（116），抛光停止器（114）和公共源极线形成区域的栅极氧化物层。 导电材料沉积在其上。 平面化处理通过化学机械抛光工艺进行。 用于控制栅极的多晶硅层通过执行回蚀工艺而被曝光。 在栅极图案（120）和公共源极线上形成硅化物层（118A）。
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公开(公告)号：KR100443084B1
公开(公告)日：2004-08-04
申请号：KR1020010058749
申请日：2001-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76838 , H01L21/7684
Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.
Abstract translation: 在用于抛光Cu金属层的方法和设备以及用于形成Cu金属布线的方法中，从晶片去除由Cu金属层的表面氧化产生的Cu氧化物。 抛光Cu氧化物的Cu金属层被抛光。 通过使用上述方法抛光Cu金属层，可以防止在随后的抛光期间由于存在残留的Cu氧化物而导致的工艺失败，例如划痕。
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公开(公告)号：KR1020040058651A
公开(公告)日：2004-07-05
申请号：KR1020020085008
申请日：2002-12-27
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: PURPOSE: A semiconductor wafer having an MP(Monitoring Point) is provided to secure the reliability of verification for an etching and CMP(Chemical Mechanical Polishing) process by forming the first and second MPs in a wafer. CONSTITUTION: A semiconductor wafer(30) is provided with a plurality of semiconductor device regions(32) and chip cut regions(34) for defining the semiconductor device regions. The semiconductor wafer further includes a plurality of first MPs(35) in each chip cut region for measuring the thickness of an etched oxide layer for the verification of an etching process and a plurality of second MPs(33) between the first MPs in the chip cut region for measuring the thickness of a polished oxide layer for the verification of a CMP process. The first MP is spaced apart from the second MP.
Abstract translation: 目的：提供具有MP（监测点）的半导体晶片，以通过在晶片中形成第一和第二MP来确保用于蚀刻和CMP（化学机械抛光）工艺的验证的可靠性。 构成：半导体晶片（30）设置有用于限定半导体器件区域的多个半导体器件区域（32）和切屑区域（34）。 半导体晶片还包括在每个切屑区域中的多个第一MP（35），用于测量用于验证蚀刻工艺的蚀刻氧化物层的厚度，以及芯片中的第一MP之间的多个第二MP（33） 用于测量抛光氧化物层的厚度以用于CMP过程的验证。 第一MP与第二MP间隔开。
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公开(公告)号：KR1020030075580A
公开(公告)日：2003-09-26
申请号：KR1020020014865
申请日：2002-03-19
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a metal line using a damascene process is provided to be capable of uniformly conserving the thickness of an insulating layer by using a diffusion barrier as a polish stop layer when carrying out a CMP(Chemical Mechanical Polishing) process. CONSTITUTION: The first and second insulating layer(101,103) are sequentially formed at the upper portion of a semiconductor substrate for forming a multilayer dielectric including a damascene pattern(105). A diffusion barrier(107) is formed at the resultant structure. Then, a copper layer(109) is thickly formed for filling the resultant structure. The first CMP process is carried out at the copper layer by using the diffusion barrier as a polish stop layer. Then, the polish stop layer is removed by carrying out the second CMP process for forming a copper line. Preferably, the diffusion barrier is made of TaN.
Abstract translation: 目的：提供一种使用镶嵌工艺形成金属线的方法，当进行CMP（化学机械抛光）工艺时，通过使用扩散阻挡层作为抛光停止层，能够均匀地保留绝缘层的厚度。 构成：第一和第二绝缘层（101,103）依次形成在用于形成包括镶嵌图案（105）的多层电介质的半导体衬底的上部。 在所得结构处形成扩散阻挡层（107）。 然后，厚度形成铜层（109）以填充所得到的结构。 通过使用扩散阻挡层作为抛光停止层，在铜层上进行第一CMP工艺。 然后，通过进行用于形成铜线的第二CMP工艺来去除抛光停止层。 优选地，扩散阻挡层由TaN制成。
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