公开(公告)号：KR1020130108905A

公开(公告)日：2013-10-07

申请号：KR1020120030744

申请日：2012-03-26

Applicant: 삼성전자주식회사

Inventor： 주상현 ,  박일한 ,  송기환

IPC: G11C7/10

CPC classification number: G11C11/24 ,  G11C16/02 ,  G11C16/10 ,  G11C2216/14

Abstract: PURPOSE: A page buffer, a memory device including the same, and a driving method of the memory device improve the data storage performance of a storage node by minimizing the disturbance of a storage capacitor. CONSTITUTION: A static latch (S) stores data provided from the outside. A dynamic latch (DL1) receives the data stored in the static latch through a floating node. The dynamic latch includes a storage capacitor, a write transistor (WTR), and a read transistor (RTR). The write transistor writes the data of the floating node on the storage capacitor. The read transistor reads the data of the storage capacitor. The write transistor and the read transistor share the floating node.

Abstract translation: 目的：页面缓冲器，包括该缓冲器的存储器件，以及存储器件的驱动方法，通过最小化存储电容器的干扰来提高存储节点的数据存储性能。 构成：静态锁存器（S）存储从外部提供的数据。 动态锁存器（DL1）通过浮动节点接收存储在静态锁存器中的数据。 动态锁存器包括存储电容器，写晶体管（WTR）和读晶体管（RTR）。 写晶体管将浮动节点的数据写入存储电容器。 读取晶体管读取存储电容器的数据。 写晶体管和读晶体管共享浮动节点。

公开(公告)号：KR101308046B1

公开(公告)日：2013-09-26

申请号：KR1020060132912

申请日：2006-12-22

Applicant: 삼성전자주식회사

Inventor： 박덕하 ,  송기환 ,  김진영

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

Abstract: 본 발명은 커패시터리스(capacitor-less) 동적 반도체 메모리 장치를 공개한다. 이 장치는 워드라인에 연결된 게이트들과 복수개의 비트 라인들 각각에 연결된 드레인들과 복수개의 소스 라인들 각각에 연결된 소스들을 가지는 플로팅 바디 트랜지스터를 각각 구비하는 메모리 셀들, 워드라인에 연결된 게이트와 제 1 더미 비트라인에 연결된 드레인과 제1더미 소스라인에 연결된 소스를 가지는 플로팅 바디 트랜지스터를 구비하고 데이터 “1”이 저장된 제1더미 셀, 워드라인에 연결된 게이트와 제 2 더미비트라인에 연결된 드레인과 제2더미 소스라인에 연결된 소스를 가지는 플로팅 바디 트랜지스터를 구비하고 데이터 “0”이 저장된 제2더미 셀, 등화신호에 응답해서 제 1 더미비트라인과 제 2 더미비트라인을 등화하는 등화트랜지스터, 비트라인선택신호에 응답해서 복수개의 비트라인들 중 하나를 선택하여 감지비트라인에 연� ��하는 비트라인선택기, 제1 및 제2더미비트라인선택신호들 각각에 응답해서 제 1 및 더미비트라인들중의 하나를 선택하여 반전 감지 비트라인에 연결하는 더미비트라인연결부, 및 감지 비트라인과 반전 감지 비트라인의 전압 차를 감지하여 증폭하는 센싱부로 구성되어 있다.

公开(公告)号：KR1020120040516A

公开(公告)日：2012-04-27

申请号：KR1020100101982

申请日：2010-10-19

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환 ,  오재희 ,  정지현

IPC: G11C7/12 ,  G11C7/18 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L27/2409 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2436 ,  G11C16/30 ,  G11C13/02 ,  G11C16/08 ,  G11C16/24

Abstract: PURPOSE: A memory device, a manufacturing method thereof, and a memory system including the same are provided to reduce discharge time by discharging a bit line voltage using a diode. CONSTITUTION: A memory device includes a plurality of sub cell arrays(21-1) and a switch. A plurality of sub cell arrays include a plurality of memory cells(23-1 to 23-n), a discharge line and a plurality of diodes. The plurality of memory cells are arranged in an intersection between a plurality of local bit lines and a plurality of word lines. A plurality of diodes(24) are connected between the plurality of local bit lines and the discharge line. A switch connects the discharge lien and the ground in response to a discharge enable signal.

Abstract translation: 目的：提供一种存储器件及其制造方法和包括该存储器件的存储器系统，以通过使用二极管放电位线电压来减少放电时间。 构成：存储器件包括多个子单元阵列（21-1）和开关。 多个子单元阵列包括多个存储单元（23-1至23-n），放电线和多个二极管。 多个存储单元布置在多个局部位线和多个字线之间的交叉点中。 多个二极管（24）连接在多个局部位线与放电线之间。 开关响应于放电使能信号连接放电留置和接地。

公开(公告)号：KR1020120015725A

公开(公告)日：2012-02-22

申请号：KR1020100078098

申请日：2010-08-13

Applicant: 삼성전자주식회사

Inventor： 노유환 ,  조백형 ,  송기환 ,  최영돈

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C11/4094 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

Abstract: PURPOSE: A voltage control method and a memory device using the same are provided to increase a writing operation by shortening discharge time of a write global bit line. CONSTITUTION: A memory cell array includes a plurality of global bit lines, a plurality of sub arrays, and a plurality of local bit line selection circuits. A first sub array(21-1) includes a plurality of nonvolatile memory cells(23). A first local bit line selection circuit(22-1) includes a plurality of switching circuits. A switching circuit connects the plurality of global bit liens to a discharge line in response to a discharge enable signal. A first discharge circuit supplies a first voltage to the discharge line. The first voltage is higher than a ground voltage.

Abstract translation: 目的：提供电压控制方法和使用其的存储器件，以通过缩短写入全局位线的放电时间来增加写入操作。 构成：存储单元阵列包括多个全局位线，多个子阵列和多个局部位线选择电路。 第一子阵列（21-1）包括多个非易失性存储单元（23）。 第一局部位线选择电路（22-1）包括多个开关电路。 开关电路响应于放电使能信号将多个全局位留置器连接到放电线。 第一放电电路向放电线提供第一电压。 第一电压高于接地电压。

公开(公告)号：KR1020100070157A

公开(公告)日：2010-06-25

申请号：KR1020080128771

申请日：2008-12-17

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  탁남균

IPC: G11C16/34 ,  G11C29/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: H01L23/5252 ,  G11C17/18 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A transistor dielectric rupture type anti-fuse utilizing chisel or CHISHL, and program circuit having it are provided to program data under low voltage by destructing a dielectric adjacent to a drain of a transistor. CONSTITUTION: A substrate(15) has a first conductivity type. A source(13) and drain(14) have a second conductive type and are separated from a predetermined domain within a substrate. A dielectric(12) is formed between source and drain on the top of substrate. The transistor comprises a gate(11) formed on the top of the dielectric. The dielectric between the gate and the substrate which is adjacent to the drain is destroyed.

Abstract translation: 目的：提供一种使用凿子或CHISHL的晶体管介质断裂型抗熔丝及其编程电路，通过破坏与晶体管的漏极相邻的电介质来在低电压下编程数据。 构成：衬底（15）具有第一导电类型。 源极（13）和漏极（14）具有第二导电类型并且与衬底内的预定域分离。 在衬底顶部的源极和漏极之间形成电介质（12）。 晶体管包括形成在电介质顶部上的栅极（11）。 与漏极相邻的栅极和衬底之间的电介质被破坏。

公开(公告)号：KR1020100053827A

公开(公告)日：2010-05-24

申请号：KR1020080112635

申请日：2008-11-13

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  박철우 ,  송기환

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C11/4099 ,  G11C11/4091

Abstract: PURPOSE: A semiconductor memory device is provided to accurately read data regardless of data value saved in a memory cell by making the difference of capacitance which is applied to a bit line pair larger. CONSTITUTION: A memory cell array(MA0,MA1) comprises a first memory cell, a second memory cell, a first mismatch cell, and a second mismatch cell. A sense amplifier senses the voltage difference between a bit line and an inverted bit line in response to a sense enable signal. A sense amplifier(SA) amplifies the voltage difference of the bit line pair. A pre-charger(EQ) pre-charges the bit line pair in response to a equalizer signal to the power voltage level. A PMOS sense amplifier comprises two PMOS transistors whose current driving capabilities are same. A NMOS sense amplifier comprises two NMOS transistors whose current driving capabilities are same.

Abstract translation: 目的：提供一种半导体存储器件，用于通过使施加到位线对的电容差较大来精确地读取数据，而不管存储器单元中保存的数据值。 构成：存储单元阵列（MA0，MA1）包括第一存储单元，第二存储单元，第一不匹配单元和第二不匹配单元。 感测放大器响应于感测使能信号来感测位线和反相位线之间的电压差。 读出放大器（SA）放大位线对的电压差。 预充电器（EQ）响应于均衡器信号对电源电压电平预充电位线对。 PMOS读出放大器包括两个PMOS晶体管，其当前驱动能力相同。 NMOS读出放大器包括两个NMOS晶体管，其当前驱动能力相同。

公开(公告)号：KR1020100052907A

公开(公告)日：2010-05-20

申请号：KR1020080111797

申请日：2008-11-11

Applicant: 삼성전자주식회사

Inventor： 정회주 ,  송기환

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/005

Abstract: PURPOSE: A semiconductor memory device is provided to reduce the number of signals outputted from a column decoder by selecting a plurality of bit lines in response to a bit line selection indication signal of a bit line selector. CONSTITUTION: A memory cell array(110) comprises a plurality of memory cells between a word line and a bit line. A column decoder(120) outputs a bit line selection indication signal in response to a column address. A bit line selector(130) selects, activates, and outputs the bit line selection signal in response to the bit line selection indication signal. One end of a switch is connected to a bit line. The other end is successively connected to a sensing line. A shared sense amplifier(140) comprises a sense amplifier sensing and amplifying data applied through the sensing line.

Abstract translation: 目的：提供一种半导体存储器件，用于通过选择位线选择器的位线选择指示信号来选择多个位线来减少从列解码器输出的信号数量。 构成：存储单元阵列（110）包括字线和位线之间的多个存储单元。 列解码器（120）响应于列地址输出位线选择指示信号。 位线选择器（130）响应于位线选择指示信号选择，激活和输出位线选择信号。 开关的一端连接到位线。 另一端依次连接到感测线。 共享读出放大器（140）包括感测放大器，用于感测和放大通过感测线施加的数据。

公开(公告)号：KR1020090126879A

公开(公告)日：2009-12-09

申请号：KR1020080053217

申请日：2008-06-05

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환

IPC: G11C7/10 ,  G11C5/14

CPC classification number: H03K19/018521 ,  G11C8/08 ,  G11C11/4085

Abstract: PURPOSE: A driver circuit having high reliability and driving capacity and a semiconductor memory device including the same are provided to solve a reliability problem of a transistor generated in the driver circuit by forming a circuit compromising advantages of the driver circuits. CONSTITUTION: A driver circuit(10) drives an output node through first power voltage or second power voltage in response to an input signal. The driver circuit comprises a pull-up unit(12), an interface unit(14) and a pull-down unit(20). The pull-up unit is connected between the first power voltage and the output node. The pull-up unit forms a current path between the output node and the first power voltage in response to the input signal. The interface unit is connected between the output node and a first node. The interface unit reduces voltage of the first node in response to a control signal. The interface unit comprises a first transistor(16) and a first resistance(R1). The pull-down unit is connected between the first node and the second power voltage. The pull-down unit forms an electrical path between the second power voltage and the first node in response to the input signal.

Abstract translation: 目的：提供具有高可靠性和驱动能力的驱动器电路以及包括该驱动电路的半导体存储器件，以通过形成有利于驱动器电路的优点的电路来解决在驱动电路中产生的晶体管的可靠性问题。 构成：响应于输入信号，驱动电路（10）通过第一电源电压或第二电源电压来驱动输出节点。 驱动器电路包括上拉单元（12），接口单元（14）和下拉单元（20）。 上拉单元连接在第一电源电压和输出节点之间。 上拉单元响应于输入信号在输出节点和第一电源电压之间形成电流路径。 接口单元连接在输出节点和第一个节点之间。 接口单元响应于控制信号而减小第一节点的电压。 接口单元包括第一晶体管（16）和第一电阻（R1）。 下拉单元连接在第一节点和第二电源电压之间。 下拉单元响应于输入信号在第二电源电压和第一节点之间形成电路径。

公开(公告)号：KR1020080058798A

公开(公告)日：2008-06-26

申请号：KR1020060132902

申请日：2006-12-22

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환 ,  박덕하

IPC: G11C11/4094 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4016

Abstract: A capacitor-less dynamic semiconductor memory device and a method of operating the same are provided to suppress the increase of memory size, by using a shared bit line voltage sense amplifier directly sensing and amplifying voltage difference generated in bit lines. A memory block(410) includes memory cells comprising a floating body transistor having a gate connected to a word line, a drain connected to each of a number of bit line pairs and a source connected to a source line. A bit line selection part(420) connects one of the bit line pairs to a middle bit line pair in response to bit line selection signals. At least two sense amplification parts sense and amplify voltage difference of each sensing bit line pair. A control part connects the middle bit line pair to a sensing bit line pair of the two sense amplification parts in turn.

Abstract translation: 提供一种无电容动态半导体存储器件及其操作方法，通过使用共享的位线电压读出放大器来直接感测和放大在位线中产生的电压差来抑制存储器大小的增加。 存储器块（410）包括存储器单元，其包括具有连接到字线的栅极的浮动体晶体管，连接到多个位线对中的每一个的漏极和连接到源极线的源极。 位线选择部分（420）响应于位线选择信号将位线对之一连接到中间位线对。 至少两个感测放大部分感测和放大每个感测位线对的电压差。 控制部分依次将中间位线对连接到两个感测放大部分的感测位线对。

公开(公告)号：KR100801707B1

公开(公告)日：2008-02-11

申请号：KR1020060126831

申请日：2006-12-13

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A floating-body memory and a method for fabricating the same are provided to reduce junction capacitance by arranging leakage shielding patterns between a floating body and first source/drain regions. A semiconductor substrate(11) includes a cell region and a peripheral region. A floating body memory cell is arranged on the cell region of the semiconductor substrate. A first floating body(22) is arranged on the peripheral region of the semiconductor substrate. A peripheral gate pattern(48) is arranged on the first floating body. A plurality of first source/drain regions(58,60) are arranged at both sides of the peripheral gate pattern. A plurality of first leakage shielding patterns(52P) are arranged between the first floating body and the first source/drain regions. The first source/drain regions contact with the first floating body.

Abstract translation: 提供浮体存储器及其制造方法，以通过在浮体和第一源极/漏极区域之间布置泄漏屏蔽图案来减小结电容。 半导体衬底（11）包括单元区域和周边区域。 在半导体衬底的单元区域上布置浮体存储单元。 第一浮体（22）布置在半导体衬底的周边区域上。 外围门图案（48）布置在第一浮体上。 多个第一源极/漏极区域（58,60）布置在外围栅极图案的两侧。 多个第一泄漏屏蔽图案（52P）布置在第一浮体和第一源极/漏极区之间。 第一源极/漏极区域与第一浮体接触。