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公开(公告)号：KR101556641B1
公开(公告)日：2015-10-02
申请号：KR1020080138534
申请日：2008-12-31
Applicant: 삼성전자주식회사
IPC: H01L21/8238
CPC classification number: H01L21/823842 , H01L21/82385
Abstract: 문턱전압을낮출수 있는듀얼게이트반도체장치의제조방법을개시한다. 본발명의듀얼게이트반도체장치의제조방법은서로다른도전형의모스트랜지스터들이형성될제1 영역및 제2 영역을구비하는반도체기판을제공하고, 상기반도체기판위에게이트유전막을형성한다. 상기게이트유전막위에제1 금속성도전층및 제2 금속성도전층을순차적으로형성한다. 상기제2 영역을마스크로가리고, 상기제1 영역의상기제1 금속성도전층에 제1 물질의이온주입을수행한다. 상기제1 영역의상기제2 금속성도전층을제거한다. 상기제1 영역의상기게이트유전막및 상기제1 금속성도전층및 상기제2 영역의상기게이트유전막, 상기제1 금속성도전층및 상기제2 금속성도전층을패터닝하여상기제1 영역의제1 게이트전극및 상기제2 영역의제2 게이트전극을형성한다.
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公开(公告)号：KR1020100043934A
公开(公告)日：2010-04-29
申请号：KR1020080103197
申请日：2008-10-21
Applicant: 삼성전자주식회사
IPC: H01L21/324 , H01L21/3105
CPC classification number: H01L21/823842 , H01L21/82345 , H01L21/823462 , H01L21/823857
Abstract: PURPOSE: A semiconductor devices and methods of forming the same are provided to improve the electrical property of a metal oxide by supplying an oxygen in the sacrificial oxide to a metal oxide. CONSTITUTION: A metal oxide layer is formed on a substrate(100) as a single layer or a multilayer. A sacrificial oxide is formed on the metal oxide layer. A thermal treatment process on the substrate having the sacrificial oxide. In the thermal treatment process, a free energy of the sacrificial oxide is higher than that of the metal oxide.
Abstract translation: 目的：提供半导体器件及其形成方法，以通过将牺牲氧化物中的氧供给到金属氧化物来改善金属氧化物的电性能。 构成：金属氧化物层作为单层或多层形成在基板（100）上。 在金属氧化物层上形成牺牲氧化物。 在具有牺牲氧化物的衬底上的热处理工艺。 在热处理过程中，牺牲氧化物的自由能高于金属氧化物的自由能。
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公开(公告)号：KR100652354B1
公开(公告)日：2006-11-30
申请号：KR1019990039549
申请日：1999-09-15
Applicant: 삼성전자주식회사
Inventor： 조학주
IPC: H01L27/108
Abstract: 하부전극과 콘택 플러그 사이에 낮은 접촉 저항을 갖는 반도체 장치의 커패시터 및 그 제조방법이 개시되어 있다. 본 발명은 층간 절연막을 사이에 두고 기판과 연결되어 있고 강유전막을 구비하는 반도체 장치의 커패시터에 있어서, 상기 층간 절연막에 상기 기판이 노출되는 콘택홀이 형성되어 있고, 상기 콘택홀은 상기 커패시터의 하부전극과 연결되는 도전성 플러그로 채워져 있되, 적어도 상기 도전성 플러그의 상층부는 금속 실리사이드막인 것을 특징으로 하는 반도체 장치의 커패시터를 제공한다. 여기서, 상기 금속 실리사이드막은 내 산화성이 있는 코발트 또는 니켈 실리사이드막이며 하부전극이나 도전성 플러그 일부 또는 전체를 구성한다.
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公开(公告)号：KR100650698B1
公开(公告)日：2006-11-27
申请号：KR1020050070499
申请日：2005-08-02
Applicant: 삼성전자주식회사
IPC: H01L27/092 , H01L27/088 , H01L21/8238
Abstract: A method for manufacturing a semiconductor device is provided to restrain the degradation of dielectric characteristics and to control uniformly the thickness of first and second metallic gates using an enhanced dual gate structure. A dielectric film(102a,102b) is formed on a semiconductor substrate(100). A first metallic conductive layer with a first thickness is formed on the dielectric film. An etch rate of the first metallic conductive layer is decreased by annealing. A second metallic conductive layer with a second thickness larger than the first thickness is formed on the first metallic conductive layer. The second metallic conductive layer is selectively removed from a second region of the substrate by using an etch selectivity between the first and second metallic conductive layers. At this time, a first gate stack structure(115) with a first metallic gate(110) is formed on a first region of the substrate and a second gate stack structure(120) with a second metallic gate(104b) is formed on the second region of the substrate.
Abstract translation: 提供了一种用于制造半导体器件的方法，以抑制介电特性的退化并且使用增强的双栅极结构来均匀地控制第一和第二金属栅极的厚度。 介电膜（102a，102b）形成在半导体衬底（100）上。 具有第一厚度的第一金属导电层形成在电介质膜上。 第一金属导电层的刻蚀速率通过退火而降低。 在第一金属导电层上形成具有大于第一厚度的第二厚度的第二金属导电层。 通过使用第一和第二金属导电层之间的蚀刻选择性，从衬底的第二区域选择性地去除第二金属导电层。 此时，具有第一金属栅极（110）的第一栅极堆叠结构（115）形成在衬底的第一区域上，具有第二金属栅极（104b）的第二栅极堆叠结构（120）形成在 衬底的第二区域。
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Patent Agency Ranking
公开(公告)号：KR100438769B1
公开(公告)日：2004-12-17
申请号：KR1019970067072
申请日：1997-12-09
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: PURPOSE: A method for forming a metal oxide thin film of a semiconductor device by CVD(chemical vapor deposition) method is provided to embody high capacitance by using a Ti-based oxide ferroelectric layer as a dielectric layer of a capacitor. CONSTITUTION: A Ti source that is formed by melting Ti(C11H19O2)2(O-t-C4H9)2 with a solvent and an additive source are evaporated to form reaction gas. The evaporated reaction gas is transferred to the upper surface of a semiconductor substrate by using carrier gas to form a Ti-based oxide ferroelectric layer on the semiconductor substrate.
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公开(公告)号：KR100351056B1
公开(公告)日：2002-09-05
申请号：KR1020000035708
申请日：2000-06-27
Applicant: 삼성전자주식회사
Inventor： 조학주
IPC: H01L27/105
Abstract: 본 발명은 선택적 금속산화막 형성단계를 구비하는 반도체 소자의 제조방법에 대한 것이다. 본 발명에 따른 반도체 소자 제조방법은 먼저, 산소원자를 포함하고 소정 부위가 외부로 노출된 절연막을 반도체 기판에 제공한다. 그런 다음, 산소와 반응성이 있는 금속 전구가스(metal precursor)에 상기 반도체 기판을 노출시켜 상기 절연막의 노출면 상에 소정 두께의 금속산화막을 선택적으로 형성한다.
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公开(公告)号：KR1020020009974A
公开(公告)日：2002-02-02
申请号：KR1020000043682
申请日：2000-07-28
Applicant: 삼성전자주식회사
Inventor： 조학주
IPC: H01L27/105
Abstract: PURPOSE: A method for manufacturing a capacitor of a ferroelectric memory device is provided to prevent contact resistance between a capacitor and a conductive plug from being affected by a heat treatment process, by performing the heat treatment process after the second conductive layer for an upper electrode is formed. CONSTITUTION: The first conductive layer for a lower electrode is formed on a semiconductor substrate(11). A ferroelectric layer is formed on the first conductive layer. The second conductive layer for the upper electrode is formed on the ferroelectric layer. A heat treatment process is performed regarding the resultant structure having the second conductive layer. The first conductive layer, the ferroelectric layer and the second conductive layer are patterned to form the lower electrode(17a), a ferroelectric pattern(19a) and the upper electrode(23).
Abstract translation: 目的：提供一种用于制造铁电存储器件的电容器的方法，用于防止电容器和导电插塞之间的接触电阻受热处理工艺的影响，通过在用于上电极的第二导电层之后进行热处理工艺 形成了。 构成：用于下电极的第一导电层形成在半导体衬底（11）上。 在第一导电层上形成铁电层。 用于上电极的第二导电层形成在铁电层上。 对具有第二导电层的结构进行热处理。 将第一导电层，铁电层和第二导电层图案化以形成下电极（17a），铁电图案（19a）和上电极（23）。
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公开(公告)号：KR1020010029442A
公开(公告)日：2001-04-06
申请号：KR1019990065074
申请日：1999-12-29
Applicant: 삼성전자주식회사
IPC: H01L27/105
Abstract: PURPOSE: A semiconductor memory device including a capacitor protection layer is to provide a capacitor protection layer and/or a material layer for low resistance contact which prevents a capacitor dielectric from being degraded by impurity diffusion. CONSTITUTION: A capacitor includes a storage electrode(122), a plate electrode(126) and a capacitor dielectric layer(124) inserted between the storage electrode and the plate electrode. A multi encapsulating layer(EL) includes a material layer composed of at least two different insulating materials, surrounding the entire surface of the capacitor. An insulating layer is formed on the multi encapsulating layer. A metal contact(136) penetrates the multi encapsulating layer and the insulating layer to contact the plate electrode.
Abstract translation: 目的：包括电容器保护层的半导体存储器件是提供用于低电阻接触的电容器保护层和/或材料层，其防止电容器电介质由于杂质扩散而劣化。 构成：电容器包括插入存储电极和平板电极之间的存储电极（122），平板电极（126）和电容器介电层（124）。 多封装层（EL）包括由至少两种不同的绝缘材料构成的材料层，其围绕电容器的整个表面。 绝缘层形成在多封装层上。 金属接触件（136）穿透多个封装层和绝缘层以接触平板电极。
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公开(公告)号：KR1020000014388A
公开(公告)日：2000-03-15
申请号：KR1019980033792
申请日：1998-08-20
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: PURPOSE: A ferroelectric memory capacitor and forming method thereof are provided to compensate a negative electric charge reduced according to oxygen vacancy. CONSTITUTION: The capacitor comprises a lower electrode, a ferroelectric layer formed on the lower electrode and an upper electrode formed on the ferroelectric layer. A first doping layer is formed between the lower electrode and the ferroelectric layer and having an atom to compensate a negative electric charge according to oxygen vacancy generated in the ferroelectric layer. A second doping layer is formed between the ferroelectric layer and the upper layer and having an atom to compensate a negative electric charge according to oxygen vacancy generated in the ferroelectric layer.
Abstract translation: 目的：提供铁电存储电容器及其形成方法，以补偿根据氧空位而减少的负电荷。 构成：电容器包括下电极，形成在下电极上的铁电层和形成在铁电层上的上电极。 在下电极和铁电层之间形成第一掺杂层，并且具有根据铁电层中产生的氧空位补偿负电荷的原子。 在铁电层和上层之间形成第二掺杂层，并且具有根据铁电层中产生的氧空位补偿负电荷的原子。
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