公开(公告)号：KR1020100027949A

公开(公告)日：2010-03-11

申请号：KR1020090050491

申请日：2009-06-08

Applicant: 삼성전자주식회사

Inventor： 박정희 ,  하용호 ,  김도형 ,  박준상 ,  박혜영 ,  권현숙

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/04 ,  G11C13/0004 ,  H01L21/76205 ,  H01L45/1233 ,  H01L45/141

Abstract: PURPOSE: A variable resistance memory device and a method for manufacturing the same are provided to reduce an operational current of the memory device by improving the shape of a variable resistance pattern. CONSTITUTION: A variable resistance device includes a plurality of lower electrodes(132), a trench(142), a variable resistance pattern(152) and an upper electrode(175). The upper side of the lower electrodes is exposed by the trench. The variable resistance pattern includes a lower part and side parts. The lower part is contacted to the upper side of the lower electrodes. The side parts which are connected to the edge part of the lower part cover the both walls of the trench. The upper electrode is formed on the upper side of the variable resistance pattern.

Abstract translation: 目的：提供可变电阻存储器件及其制造方法，以通过改善可变电阻图案的形状来减小存储器件的工作电流。 构成：可变电阻装置包括多个下电极（132），沟槽（142），可变电阻图案（152）和上电极（175）。 下部电极的上侧被沟槽露出。 可变电阻图案包括下部和侧部。 下部与下部电极的上侧接触。 连接到下部的边缘部分的侧部覆盖沟槽的两个壁。 上电极形成在可变电阻图案的上侧。

公开(公告)号：KR1020090103566A

公开(公告)日：2009-10-01

申请号：KR1020080029249

申请日：2008-03-28

Applicant: 삼성전자주식회사

Inventor： 박정희 ,  하용호 ,  안형근 ,  박준상 ,  권현숙 ,  강명진 ,  박두환

IPC: H01L21/28

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1666

Abstract: PURPOSE: A contact structure, a semiconductor device using the same, and a manufacturing method thereof are provided to form a stable contact on an information storage pattern having a concave region in a top surface. CONSTITUTION: A contact structure includes a bottom pattern, a flattened buffer pattern(126), and a conductive pattern(131). The bottom pattern is formed on a substrate(100), and has a concave region in a top surface. The flattened buffer pattern is formed on the information storage pattern. The conductive pattern is formed on the flattened buffer pattern, and is self-aligned with the bottom pattern.

Abstract translation: 目的：提供一种接触结构，使用其的半导体器件及其制造方法，以在上表面具有凹区的信息存储图案上形成稳定的接触。 构成：接触结构包括底部图案，扁平缓冲图案（126）和导电图案（131）。 底部图案形成在基板（100）上，并且在顶面具有凹形区域。 扁平缓冲图案形成在信息存储图案上。 导电图案形成在扁平缓冲图案上，并且与底部图案自对准。

公开(公告)号：KR1020090013419A

公开(公告)日：2009-02-05

申请号：KR1020070077510

申请日：2007-08-01

Applicant: 삼성전자주식회사

Inventor： 강명진 ,  하용호 ,  박두환 ,  박정희 ,  신희주

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683 ,  Y10T428/24273 ,  H01L45/143

Abstract: A phase change memory device and a method of forming the same are provided to prevent the characteristic deterioration of the phase change material layer by filling the opening with the phase change material layer. The insulating layer(110) is arranged on the substrate(100). The insulating layer comprises the oxide film. The bottom electrode(120) can fill up the lower part of the opening(115). The bottom electrode is electrically connected to the substrate having the selection element. The phase change material pattern is arranged within the opening. The wetting pattern is interposed between the side wall of the opening and phase change material pattern(130a). The phase change material pattern contacts with the wetting pattern. The wetting pattern is extended and interposed between the phase change material pattern and the bottom electrode. The phase change material pattern and bottom electrode are electrically connected through the wetting pattern.

Abstract translation: 提供了相变存储器件及其形成方法，以通过用相变材料层填充开口来防止相变材料层的特性劣化。 绝缘层（110）设置在基板（100）上。 绝缘层包括氧化物膜。 底部电极（120）可以填充开口（115）的下部。 底部电极与具有选择元件的基板电连接。 相变材料图案布置在开口内。 润湿图案介于开口的侧壁和相变材料图案（130a）之间。 相变材料图案与润湿图案接触。 润湿图案被延伸并介于相变材料图案和底部电极之间。 相变材料图案和底部电极通过润湿图案电连接。

公开(公告)号：KR1020080028657A

公开(公告)日：2008-04-01

申请号：KR1020060094225

申请日：2006-09-27

Applicant: 삼성전자주식회사

Inventor： 구봉진 ,  하용호 ,  박두환 ,  고한봉 ,  임상욱 ,  신희주

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C13/0004 ,  G11C2213/35 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1658 ,  H01L45/1675 ,  H01L45/1683

Abstract: A method for forming a phase change memory unit and a method for manufacturing a phase change memory device including a phase-change material layer are provided to reduce a set resistance and operational current and to enhance durability and a sensing margin. A contact region(105) is formed on a substrate(100). A lower electrode(140) is electrically connected to the contact region. A preliminary phase change material layer is formed on the lower electrode by using a carbon-doped chalcogenide compound or a carbon or nitrogen-doped chalcogenide compound on a lower electrode. A phase change material layer is formed by doping a stabilization metal onto the preliminary phase change material layer. An upper electrode(175) is formed on the phase change material layer. An insulating structure having at least one pad connected to the contact region is formed on the substrate before the lower electrode is formed.

Abstract translation: 提供一种用于形成相变存储单元的方法和用于制造包括相变材料层的相变存储器件的方法，以减小设定电阻和工作电流，并提高耐久性和感测裕度。 接触区域（105）形成在基板（100）上。 下电极（140）电连接到接触区域。 通过在下电极上使用碳掺杂的硫属化物化合物或碳或氮掺杂的硫族化合物，在下电极上形成初步的相变材料层。 通过将稳定化金属掺杂到初始相变材料层上来形成相变材料层。 在相变材料层上形成上电极（175）。 在形成下电极之前，在基板上形成具有连接到接触区域的至少一个焊盘的绝缘结构。

公开(公告)号：KR100807230B1

公开(公告)日：2008-02-28

申请号：KR1020060094208

申请日：2006-09-27

Applicant: 삼성전자주식회사

Inventor： 구봉진 ,  하용호 ,  고한봉 ,  박두환 ,  신희주 ,  임상욱

IPC: H01L27/115

CPC classification number: H01L45/1233 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683

Abstract: A phase-change material layer and a phase-change memory device having the same are provided to effectively reduce an operation current of the device, without increasing set resistance. A substrate(100) has contact regions(121,124), and an interlayer dielectric(127) is formed on the substrate. A bottom electrode(163) is electrically connected to the contact region. At least one pad penetrates the interlayer dielectric to electrically connect the bottom electrode with the contact region. A phase-change material layer pattern is formed on the bottom electrode, and comprises a chalcogenide compound doped with at least one of nitrogen and metal. A top electrode is formed on the phase-change material layer pattern.

Abstract translation: 提供了相变材料层和具有该相变材料层的相变存储器件，以有效地降低器件的工作电流，而不增加设定电阻。 基板（100）具有接触区域（121,124），并且在基板上形成层间电介质（127）。 底部电极（163）电连接到接触区域。 至少一个焊盘穿透层间电介质以将底部电极与接触区域电连接。 在底部电极上形成相变材料层图案，并且包括掺杂有氮和金属中至少一种的硫族化合物。 在相变材料层图案上形成顶部电极。

公开(公告)号：KR100504697B1

公开(公告)日：2005-08-03

申请号：KR1020030017237

申请日：2003-03-19

Applicant: 삼성전자주식회사

Inventor： 하용호 ,  김현조 ,  이지혜

IPC: H01L27/10

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1666

Abstract: 감소된 접촉 영역을 구비하는 상변화 기억 셀이 개시된다. 상기 접촉 영역은 두 전극들 중 어느 한 전극의 측벽, 또는 그 전극을 관통하는 구멍의 측벽(즉 주변 가장자리)일 수 있다. 따라서, 상기 전극의 두께가 얇으면, 상기 전극 및 상변화 물질 패턴 사이의 접촉 영역이 매우 작게 된다. 결과적으로, 상변화 기억 소자의 전력 소모를 줄일 수 있고 신뢰성 있고 간결한 상변화 기억 셀을 형성할 수 있다.

公开(公告)号：KR1020050004137A

公开(公告)日：2005-01-12

申请号：KR1020040051756

申请日：2004-07-02

Applicant: 미츠비시 마테리알 가부시키가이샤 ,  삼성전자주식회사

Inventor： 호리이히데키 ,  모리사또루 ,  하용호 ,  박정희 ,  기노시따게이 ,  노나까소헤이

IPC: H01L21/20 ,  B41M5/26 ,  G11B7/243

CPC classification number: H01L45/1625 ,  C23C14/3414 ,  G11B7/00454 ,  G11B7/243 ,  G11B2007/2431 ,  G11B2007/24312 ,  G11B2007/24314 ,  G11B2007/24328 ,  H01L45/06 ,  H01L45/144

Abstract: PURPOSE: A phase change recording layer having a high electrical resistance and a sputtering target of forming the same are provided to decrease an electric current at the time of writing and erasing operation by increasing an electrical resistance of the same. CONSTITUTION: A phase change recording layer has a high electrical resistance. The phase change recording layer includes Ge of 15 to 30 atom percent, Sb of 15 to 25 atom percent, one or both of Al and Si of a total 0.1 to 13 atom percent, and the balance of Te and impurities. The phase change recording layer has a specific resistance, which is about 5*10¬-12 to 5*10¬1 ¥Ø*cm.

Abstract translation: 目的：提供具有高电阻的相变记录层和形成该高电阻的溅射靶，以通过增加其写入和擦除操作来减小电流。 构成：相变记录层具有高电阻。 相变记录层包括15至30原子％的Ge，15至25原子％的Sb，Al和Si中的一种或两种，总计为0.1至13原子％，余量为Te和杂质。 相变记录层的电阻率约为5×10 -12至5×10 -1×Ø* cm。

公开(公告)号：KR1020040076040A

公开(公告)日：2004-08-31

申请号：KR1020030011356

申请日：2003-02-24

Applicant: 삼성전자주식회사

Inventor： 이지혜 ,  호리이히데키 ,  하용호

IPC: H01L27/10

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

Abstract: PURPOSE: A phase-change memory device having self-heater structure is provided to improve reliability by reducing a unit cell area while being not influenced by the limit of a photolithography technology and an etch technology and by uniformly controlling the operation of the device. CONSTITUTION: The first conductive layer(22) is formed on the first level on a semiconductor substrate(10). The second conductive layer(52) is formed on the second level having a different height than that of the first level on the semiconductor substrate. A phase-change memory layer(32) extends in parallel with a main surface of the semiconductor substrate, having the first surface(34) confronting the semiconductor substrate. The first contact surface(26a) is formed on the first surface of the phase-change memory layer to supply an electrical signal from the first conductive layer to the phase-change memory layer. The second contact surface(28a) is formed on the first surface of the phase-change memory layer to supply an electrical signal from the phase-change memory layer to the second conductive layer, separated from the first contact surface.

Abstract translation: 目的：提供具有自加热器结构的相变存储器件，以通过减小单位晶胞面积而不受光刻技术和蚀刻技术的限制以及通过均匀地控制器件的操作来改善可靠性。 构成：第一导电层（22）形成在半导体衬底（10）上的第一层上。 第二导电层（52）形成在具有与半导体衬底上的第一电平不同的高度的第二电平上。 相变存储层（32）与半导体衬底的主表面平行延伸，具有与半导体衬底相对的第一表面（34）。 第一接触表面（26a）形成在相变存储层的第一表面上，以将电信号从第一导电层提供给相变存储层。 第二接触表面（28a）形成在相变存储层的第一表面上，以从相变存储层向与第一接触表面分离的第二导电层提供电信号。

公开(公告)号：KR102212267B1

公开(公告)日：2021-02-04

申请号：KR1020140032248

申请日：2014-03-19

Applicant: 삼성전자주식회사

Inventor： 쩡웨이숑 ,  김주연 ,  원석준 ,  이종호 ,  이혜란 ,  하용호

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/31 ,  H01L21/324

Abstract: 반도체장치제조방법이제공된다. 반도체장치제조방법은, 기판상에트렌치를포함하는층간절연막을형성하고, 상기트렌치내에고유전율(high-k)막을형성하고, 상기고유전율막상에확산막과차단막을순차적으로형성하고, 상기기판에어닐링을수행하고, 상기차단막과상기확산막을순차적으로제거하고, 상기고유전율막상에제1 배리어막을형성하고, 상기제1 배리어막상에순차적으로일함수조절막, 제2 배리어막및 게이트메탈을형성하고, 상기게이트메탈상에캡핑막을형성하는것을포함한다.

公开(公告)号：KR1020150109159A

公开(公告)日：2015-10-01

申请号：KR1020140032248

申请日：2014-03-19

Applicant: 삼성전자주식회사

Inventor： 쩡웨이숑 ,  김주연 ,  원석준 ,  이종호 ,  이혜란 ,  하용호

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/31 ,  H01L21/324

CPC classification number: H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

Abstract: 반도체장치제조방법이제공된다. 반도체장치제조방법은, 기판상에트렌치를포함하는층간절연막을형성하고, 상기트렌치내에고유전율(high-k)막을형성하고, 상기고유전율막상에확산막과차단막을순차적으로형성하고, 상기기판에어닐링을수행하고, 상기차단막과상기확산막을순차적으로제거하고, 상기고유전율막상에제1 배리어막을형성하고, 상기제1 배리어막상에순차적으로일함수조절막, 제2 배리어막및 게이트메탈을형성하고, 상기게이트메탈상에캡핑막을형성하는것을포함한다.

Abstract translation: 提供一种半导体器件的制造方法。 制造半导体器件的方法包括以下步骤：在衬底上形成包括沟槽的层间绝缘层; 在沟槽中形成高k电介质层; 在高k电介质层上依次形成扩散层和阻挡层; 随后在衬底上进行退火; 退火后依次去除阻挡层和扩散层; 在高k电介质层上形成第一阻挡层; 在第一阻挡层上依次形成功函数控制层，第二阻挡层和栅极金属; 并在栅极金属上形成覆盖层。