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公开(公告)号：KR101714004B1
公开(公告)日：2017-03-09
申请号：KR1020100018086
申请日：2010-02-26
Applicant: 삼성전자주식회사
CPC classification number: H01L29/92
Abstract: 트랜치형의커패시터를제공할수 있다. 이를위해서, 반도체기판에제 1 및 2 활성영역들이배치될수 있다. 상기제 1 활성영역에노드패턴들이배치될수 있다. 상기노드패턴들의각각은차례로적층되는도전패턴및 절연패턴을가질수 있다. 상기노드패턴들의주변에불순물확산영역들이배치될수 있다. 상기제 1 및 2 활성영역들과전기적으로접속하는기판접속패턴들이배치될수 있다. 상기제 1 및 2 활성영역들의주변에서노드패턴들과전기적으로접속하는노드접속패턴들이배치될수 있다. 더불어서, 상기트랜치형의커패시터를포함하는반도체장치및 상기반도체장치를포함하는반도체모듈이제공될수 있다.
Abstract translation: 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。
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公开(公告)号：KR101576957B1
公开(公告)日：2015-12-14
申请号：KR1020090100765
申请日：2009-10-22
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/115 , H01L21/336
CPC classification number: H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
Abstract: 수직형반도체소자, 메모리소자, 및그 제조방법이제공된다. 수직형반도체소자는기판을포함한다. 반도체필라는상기기판상에서수직방향으로신장되고, 하부불순물영역, 상기하부불순물영역상의수직채널영역및 상기수직채널영역상의상부불순물영역을포함한다. 비트라인은상기하부불순물영역과접촉하도록상기하부불순물영역의제 1 측벽상에배치된다. 워드라인은상기수직채널영역의제 2 측벽상에서, 상기비트라인과수직하게신장되고, 상기제 2 메사부분상에이격배치된다. 게이트절연층은상기수직채널영역및 상기워드라인사이에제공된다. 또한, 상기하부불순물영역은상기비트라인위에제 2 메사부분을포함한다.
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公开(公告)号：KR101534683B1
公开(公告)日：2015-07-24
申请号：KR1020090029012
申请日：2009-04-03
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/28 , H01L21/3205
CPC classification number: H01L27/10885 , H01L27/0207 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897
Abstract: 반도체장치및 그의형성방법을제공할수 있다. 이를위해서, 반도체기판상에셀 비트라인패턴및 주변게이트패턴을형성할수 있다. 상기셀 비트라인패턴은반도체기판의셀 활성영역주변의비활성영역상에배치될수 있다. 상기주변게이트패턴은반도체기판의주변활성영역상에배치될수 있다. 상기셀 비트라인패턴및 셀활성영역사이에셀 콘택플러그를형성할수 있다. 상기주변게이트패턴의측부에위치하도록주변활성영역상에주변콘택플러그가배치될수 있다. 상기셀 비트라인패턴, 주변게이트패턴, 셀및 주변콘택플러그들의상면들을실질적으로동일레벨에서노출시키는절연막이배치될수 있다.
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公开(公告)号：KR1020140108935A
公开(公告)日：2014-09-15
申请号：KR1020130022848
申请日：2013-03-04
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L23/544 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L27/0688 , H01L27/10897 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L2221/68327 , H01L2221/6835 , H01L2221/68363 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
Abstract: The present invention relates to semiconductor devices and methods for fabricating the same. The methods for fabricating the semiconductor devices comprise the steps of: supplying a semiconductor substrate having a first surface and a second surface as an opposite surface; forming an alignment key and an interconnection partially passing through the semiconductor substrate and extended from the first surface to the second surface; forming a first circuit arranged on the first surface of the semiconductor substrate and electrically coupled with the interconnection; forming a third surface exposing the alignment key and the interconnection by recessing the second surface of the semiconductor substrate; and forming a second circuit arranged on the third surface of the semiconductor substrate and electrically coupled with the interconnection.
Abstract translation: 本发明涉及半导体器件及其制造方法。 制造半导体器件的方法包括以下步骤：提供具有第一表面和第二表面的半导体衬底作为相对表面; 形成对准键和部分穿过半导体衬底并从第一表面延伸到第二表面的互连; 形成布置在所述半导体衬底的所述第一表面上并与所述互连电耦合的第一电路; 通过使所述半导体衬底的所述第二表面凹陷来形成暴露所述对准键和所述互连的第三表面; 以及形成布置在所述半导体衬底的所述第三表面上并与所述互连电连接的第二电路。
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公开(公告)号：KR1020130039062A
公开(公告)日：2013-04-19
申请号：KR1020110103500
申请日：2011-10-11
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/10885 , H01L27/10855 , H01L27/10876 , H01L27/10888
Abstract: PURPOSE: A semiconductor device including a vertical channel transistor, and a method for fabricating the same are provided to form a buried bit line between surround gate electrodes, and to remove a coupling noise between adjacent surround gate electrodes. CONSTITUTION: A lower active part(BAR) is protruded from a substrate. Active pillars are protruded from the lower active part. A surround gate electrode(SG) surrounds the active pillars. A buried bit line is arranged between adjacent surround gate electrodes. A contact gate electrode(CG) is extended to a second direction to touch a word line(WL).
Abstract translation: 目的：提供一种包括垂直沟道晶体管的半导体器件及其制造方法，以在环绕栅电极之间形成掩埋位线，并消除相邻环绕栅电极之间的耦合噪声。 构成：下部活性部分（BAR）从基底突出。 活动柱从下部活动部分突出。 环绕门电极（SG）包围有源支柱。 掩埋位线布置在相邻环绕栅电极之间。 接触栅电极（CG）延伸到第二方向以接触字线（WL）。
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Patent Agency Ranking
公开(公告)号：KR1020120050820A
公开(公告)日：2012-05-21
申请号：KR1020100112260
申请日：2010-11-11
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L29/78 , H01L29/10 , H01L29/66
CPC classification number: H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831 , H01L27/10882
Abstract: PURPOSE: A semiconductor device which includes a vertical channel transistor and a manufacturing method thereof are provided to arrange a body contact which is directly connected to a vertical channel, thereby providing a movement route of a hole piled on the vertical channel to a semiconductor substrate. CONSTITUTION: A word line(170) is extended to a first horizontal direction from the upper part of a semiconductor substrate(100). The word line is divided into a pillar shape vertical gate(174) and an extension line(172). A bit line(120) is extended in a second horizontal direction between the semiconductor substrate and the word line. An active pillar(110) is arranged respectively vertical to the bit line and the word line. A capacitor(180) is electrically connected to a vertical channel transistor(10) through a contact plug(182).
Abstract translation: 目的：提供一种包括垂直沟道晶体管及其制造方法的半导体器件，用于布置直接连接到垂直沟道的主体接触，从而将垂直沟道上堆叠的孔的移动路径提供给半导体衬底。 构成：字线（170）从半导体衬底（100）的上部延伸到第一水平方向。 字线被分成柱形垂直门（174）和延伸线（172）。 位线（120）在半导体衬底和字线之间的第二水平方向上延伸。 主动柱（110）分别垂直于位线和字线布置。 电容器（180）通过接触插头（182）电连接到垂直沟道晶体管（10）。
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公开(公告)号：KR1020100092241A
公开(公告)日：2010-08-20
申请号：KR1020090011527
申请日：2009-02-12
Applicant: 삼성전자주식회사
Inventor： 홍형선
IPC: H01L21/336 , H01L21/8242
Abstract: PURPOSE: It etches the peripheral area of substrate and the manufacturing method of the semiconductor device forms so that the peripheral area and cell region have the level difference. The height of the contact connected to the imbedded transistor formed in the cell region is reduced. CONSTITUTION: In the substrate(100), the surface of the peripheral area has the level difference lower than the surface of the cell region(C). First gate structure below buried the surface of substrate is formed in the cell region of substrate. The second gate structure is formed on the peripheral area of substrate. The first gate structure and the inter-layer insulating film(120) covering the second gate structure are formed in the top of the substrate.
Abstract translation: 目的：蚀刻基板的周边区域，半导体器件的制造方法形成为使得外围区域和单元区域具有电平差。 连接到形成在单元区域中的嵌入晶体管的触点的高度减小。 构成：在基板（100）中，周边区域的表面的电平差低于电池区域（C）的表面。 在基板的单元区域中形成下面掩埋基板表面的第一栅极结构。 第二栅极结构形成在衬底的周边区域上。 覆盖第二栅极结构的第一栅极结构和层间绝缘膜（120）形成在基板的顶部。
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公开(公告)号：KR100843716B1
公开(公告)日：2008-07-04
申请号：KR1020070048763
申请日：2007-05-18
Applicant: 삼성전자주식회사
IPC: H01L21/768
CPC classification number: H01L27/10888 , H01L21/76897 , H01L27/10855
Abstract: A method for fabricating a semiconductor device having a self-aligned contact plug and a device related thereto are provided to obtain a sufficient process margin by forming a contact plug to exposing a semiconductor substrate. A lower insulating layer(69) is formed on a semiconductor substrate(50). A plurality of wiring patterns are formed in parallel to each other on the lower insulating layer. An upper insulating layer is formed to fill a gap between the wiring patterns. A plurality of first mask patterns are formed across the wiring patterns on the semiconductor substrate having the upper insulating layer. A second mask pattern is formed between the first mask patterns. A plurality of contact holes for exposing the semiconductor substrate are formed by etching the upper insulating layer and the lower insulating layer. A contact plug(93) is formed within each of the contact holes.
Abstract translation: 提供一种制造具有自对准接触插塞及其相关装置的半导体器件的方法，以通过形成接触插头以暴露半导体衬底来获得足够的工艺余量。 在半导体衬底（50）上形成下绝缘层（69）。 多个布线图案在下绝缘层上彼此平行地形成。 形成上绝缘层以填充布线图案之间的间隙。 在具有上绝缘层的半导体衬底上的布线图案之间形成多个第一掩模图案。 在第一掩模图案之间形成第二掩模图案。 通过蚀刻上绝缘层和下绝缘层形成用于暴露半导体衬底的多个接触孔。 在每个接触孔内形成接触塞（93）。
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公开(公告)号：KR102045864B1
公开(公告)日：2019-11-18
申请号：KR1020130027105
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: H01L27/108
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