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公开(公告)号:KR1019930004712B1
公开(公告)日:1993-06-03
申请号:KR1019900008203
申请日:1990-06-04
Applicant: 한국전자통신연구원
IPC: H01L21/30
Abstract: In the device for group 5 atom of molecular-line epitaxy unit, the device is connected by the supply path (30) an upper heating section (10) formed with the opened pot furnace (11) at the upper and lower part and a lower supply section (20) with the lifting member (23) of a rotary screw type, separated by a valve (31) in the middle part. The side wall of an upper heating sect. (10) has a tantalum heater (12), is enclosed with the tantalum or molybdenum foil (13) of two or three folds, has a stopper (14) on the furnace upper part. The lower supply sect. (20) includes a vacuum pump (21), a lifting screw (26) and a tray (27).
Abstract translation: 在分子线外延单元的第5族原子的装置中,该装置通过供给路径(30)与在上部和下部形成有打开的罐式炉(11)的上部加热部(10)连接,下部 供应部分(20)具有旋转螺杆式提升构件(23),在中间部分由阀(31)分开。 上部加热段的侧壁。 (10)具有钽加热器(12),被两个或三个折叠的钽或钼箔(13)封闭,在炉上部具有止动件(14)。 较低的供应部门。 (20)包括真空泵(21),提升螺杆(26)和托盘(27)。
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公开(公告)号:KR1019940002835B1
公开(公告)日:1994-04-04
申请号:KR1019910006167
申请日:1991-04-17
Applicant: 한국전자통신연구원
IPC: H01L27/10
CPC classification number: H01L27/10864 , H01L21/76235 , H01L27/10841 , H01L29/66909 , H01L29/8083
Abstract: The structure is characterized by active regions, of the transistor, which are of the island form consisting of field oxides formed on the trench of the transistor. The drain region (16) and the word line (10) are insulated by the space (5a) and the gate is directly connected to the word line. The electrode for storing the capacitor is formed on the drain region and then the dielectric film and the plate contact are formed on the electrode. The JFET transistor and the storage capacitor are connected perpendicular to each other.
Abstract translation: 该结构的特征在于晶体管的有源区,其是由形成在晶体管的沟槽上的场氧化物构成的岛状。 漏极区域(16)和字线(10)被空间(5a)绝缘,栅极直接连接到字线。 用于存储电容器的电极形成在漏极区域上,然后在电极上形成电介质膜和板接触。 JFET晶体管和存储电容器彼此垂直连接。
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公开(公告)号:KR1019930011177B1
公开(公告)日:1993-11-24
申请号:KR1019900021809
申请日:1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L29/80
Abstract: The three layers for a vertical device isolation having several devices on a substrate is prepared by forming 1st epitaxial layer (2) for the device on a gallium arsenide substrate (1), depositing a 200-1000∦ aluminium gallium arsenide layer (3) at 640-690 deg.C thereon, depositing an insulating gallium arsenide layer (4) of a proper thickness at the low temperature of 200 deg.C, depositing a 200-1000 ∦ aluminum gallium arsenide layer (5) at 640-690 deg.C, depositing a gallium arsenide layer (7) thereon.
Abstract translation: 通过在砷化镓衬底(1)上形成用于器件的第一外延层(2),将200-1000μm的砷化铝镓层(3)沉积在第一外延层(2)上,制备用于在衬底上具有多个器件的垂直器件隔离的三层 640-690℃,在200℃的低温下沉积适当厚度的绝缘砷化镓层(4),在640-690度沉积200-1000℃的砷化铝镓层(5)。 C,在其上沉积砷化镓层(7)。
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