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公开(公告)号：KR101381056B1
公开(公告)日：2014-04-14
申请号：KR1020120137385
申请日：2012-11-29
Applicant: 전북대학교산학협력단 , 주식회사 시지트로닉스
IPC: H01L21/20
Abstract: A semiconductor substrate where a III-nitride-based epi layer is grown according to the present invention includes a substrate; a transfer layer which is formed on the substrate and molten at a preset temperature; a buffer layer which is formed on the transfer layer; and a III-nitride-based epi layer which is made of a III-nitride-based material and formed on the buffer layer. According to the present invention, provided can be a semiconductor substrate where a III-nitride-based epi layer which can solve a stress due to the lattice mismatch and the mismatch of coefficient of thermal expansion of the III-nitride-based epi layer and the semiconductor substrate by forming the transfer layer between the III-nitride-based epi layer and a semiconductor substrate and using melting properties, and a method thereof.
Abstract translation: 根据本发明生长III族氮化物的外延层的半导体衬底包括衬底; 形成在基板上并在预定温度下熔融的转印层; 形成在转印层上的缓冲层; 以及由III族氮化物系材料制成并形成在缓冲层上的III族氮化物系外延层。 根据本发明，可以提供一种半导体基板，其中可以解决由于晶格失配引起的应力和III族氮化物基外延层的热膨胀系数的失配的III族氮化物系外延层 半导体衬底，其通过在III族氮化物基外延层和半导体衬底之间形成转移层并使用熔融特性及其方法。
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公开(公告)号：KR1020130091871A
公开(公告)日：2013-08-20
申请号：KR1020120013162
申请日：2012-02-09
Applicant: 전북대학교산학협력단 , 주식회사 시지트로닉스
IPC: H01L21/20
Abstract: PURPOSE: A method for growing a III-nitride-based epi layer on a Si substrate and a semiconductor substrate thereof are provided to obtain the thermal stability of high power by using an excellent heat conduction property. CONSTITUTION: A silicon germanium epi layer (102) is grown on a silicon substrate (101). The silicon germanium epi layer is formed by injecting a high concentration impurity. A III-nitride-based epi layer (103) is grown on the silicon germanium epi layer. The silicon germanium epi layer is a Si/SiGe/Si structure. The silicon germanium epi layer includes a cap-silicon epi layer and a seed-silicon epi layer.
Abstract translation: 目的：提供一种在Si衬底及其半导体衬底上生长III族氮化物的外延层的方法，以通过使用优异的导热性获得高功率的热稳定性。 构成：在硅衬底（101）上生长硅锗外延层（102）。 通过注入高浓度杂质形成硅锗外延层。 在硅锗外延层上生长III族氮化物基外延层（103）。 硅锗外延层是Si / SiGe / Si结构。 硅锗外延层包括盖硅外延层和种子硅外延层。
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公开(公告)号：KR101099931B1
公开(公告)日：2011-12-28
申请号：KR1020090094961
申请日：2009-10-07
Applicant: 전북대학교산학협력단
IPC: H01L21/336
Abstract: 본 발명은 LDMOS 트랜지스터에 관한 것으로서, 반도체 기판, 반도체 기판에 배열된 게이트 리드 메탈, 게이트 리드 메탈의 중심에 게이트 리드 메탈과 수직하게 연결된 게이트 메탈, 중앙부가 게이트 메탈에 수직하게 접속되는 게이트 핑거, 게이트 핑거 사이에 게이트 핑거와 평행하게 배열되는 드레인 핑거, 드레인 핑거의 한쪽 끝을 드레인 핑거와 수직이 되도록 전기적으로 접속한 드레인 리드 메탈 및 게이트 핑거를 감싸고 형태로 형성된 메탈 클램프를 포함하고, 게이트 리드 메탈 아래에는 게이트 메탈과 게이트 핑거의 접속을 위한 콘택 홀(contact hole) 형성을 위해 사용되는 절연막 및 필드산화막이 형성되어 있어, 차단 주파수 f
t 와 최대 진동 주파수 f
max 가 높일 수 있으며, 소자를 격리시켜 서로 다른 기능을 하는 칩들과의 누화를 방지하고 선형성을 증가시킬 수 있는 것이다.
LDMOS 트랜지스터, RF power 트랜지스터, 셀가드링, 칩가드링-
公开(公告)号：KR1020100094224A
公开(公告)日：2010-08-26
申请号：KR1020090013547
申请日：2009-02-18
Applicant: 전북대학교산학협력단
IPC: H01L31/04
Abstract: PURPOSE: A solar cell and a method for manufacturing the same are provided to easily obtain a rear electrode type solar cell by manufacturing the solar cell at a low temperature less than or equal to 500degrees Celsius. CONSTITUTION: A textured silicon substrate(401) is prepared. A passivation layer(402) is formed on the entire surface of the textured substrate. An anti-reflection film(403) is formed on the entire surface of the passivation layer. Patterned electrodes(405, 406) are formed on the lower side of the substrate. An insulating film(404) is formed in order to secure the insulation between the electrodes. The electrodes include metal silicide.
Abstract translation: 目的：提供太阳能电池及其制造方法，通过在低于或等于500度的低温下制造太阳能电池来容易地获得后电极型太阳能电池。 构成：制备织构化的硅衬底（401）。 钝化层（402）形成在纹理化衬底的整个表面上。 在钝化层的整个表面上形成防反射膜（403）。 图案化电极（405,406）形成在基板的下侧。 形成绝缘膜（404）以确保电极之间的绝缘。 电极包括金属硅化物。
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公开(公告)号：KR1020100078859A
公开(公告)日：2010-07-08
申请号：KR1020080137238
申请日：2008-12-30
Applicant: 전북대학교산학협력단
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66893 , H01L29/7832
Abstract: PURPOSE: A junction field effect transistor and a manufacturing method thereof are provided to control the impurity diffusion to an upper and lower part of a channel layer by arranging a diffusion stop layer consisting of SiGe. CONSTITUTION: A lower epi layer(301) is formed on the top of a semiconductor substrate(300). A lower diffusion stop layer(302) is formed on the top of the lower epi layer. A channel layer(303) is formed on the top of the lower diffusion stop layer. A top diffusion stop layer(304) is formed on the top of the channel layer. A top epi layer(305) is formed on the top of the top diffusion stop layer. An isolation unit(306) is formed in the top and lower epi layer, the top, the lower diffusion stop layer and the side of the channel layer.
Abstract translation: 目的：提供结型场效应晶体管及其制造方法，通过设置由SiGe组成的扩散阻挡层来控制杂质扩散到沟道层的上部和下部。 构成：在半导体衬底（300）的顶部上形成较低的外延层（301）。 下扩散停止层（302）形成在下外延层的顶部。 沟道层（303）形成在下扩散停止层的顶部。 顶部扩散停止层（304）形成在沟道层的顶部。 顶部外延层（305）形成在顶部扩散停止层的顶部。 隔离单元（306）形成在顶部和下部外延层，顶部，下部扩散停止层和沟道层侧。
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Patent Agency Ranking
公开(公告)号：KR1020080027523A
公开(公告)日：2008-03-28
申请号：KR1020060092657
申请日：2006-09-25
Applicant: 전북대학교산학협력단
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L21/823821 , H01L27/0924 , H01L29/785
Abstract: A method for manufacturing a semiconductor device structure is provided to form a channel of the device by self-aligned epitaxial growth, thereby minimizing a sub threshold current that is a problem of a nano device. A template epitaxial layer is grown on a semiconductor substrate(ST1), and then a template is grown on the template epitaxial layer(ST2). A self-aligned epitaxial layer is deposited on the template(ST3), and then is subjected to chemical mechanical polishing(ST4). The template is removed, and then an oxide layer is formed(ST5). A gate thin film is deposited on the oxide layer(ST6). A gate pattern is formed on the gate thin film, and then the gate pattern is passivate by an insulating layer(ST7).
Abstract translation: 提供一种用于制造半导体器件结构的方法，以通过自对准外延生长形成器件的沟道，从而最小化作为纳米器件问题的次阈值电流。 在半导体衬底（ST1）上生长模板外延层，然后在模板外延层上生长模板（ST2）。 将自对准的外延层沉积在模板（ST3）上，然后进行化学机械抛光（ST4）。 除去模板，然后形成氧化物层（ST5）。 栅极薄膜沉积在氧化物层（ST6）上。 栅极图案形成在栅极薄膜上，然后栅极图案被绝缘层钝化（ST7）。
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公开(公告)号：KR100817403B1
公开(公告)日：2008-03-27
申请号：KR1020060114454
申请日：2006-11-20
Applicant: 전북대학교산학협력단
IPC: H01L29/737
CPC classification number: H01L29/7378 , H01L21/02381 , H01L21/02387 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/8249 , H01L29/045 , H01L29/0826 , H01L29/1004 , H01L29/165 , H01L29/205 , H01L29/66242
Abstract: A semiconductor device structure is provided to vary the physical and electrical characteristics of a semiconductor layer by additionally applying compressive stress or tensile stress from the outside. A bipolar semiconductor device of a heterojunction structure includes an emitter(211), an intrinsic base(212), a collector(213) and an insulation layer sidewall. A base for applying stress is selectively and epitaxially grown to apply local stress to the semiconductor device. The base can have a (311) slope(218) by a self-aligned epitaxial growth method. The semiconductor device structure can include an insulation layer(215) for applying stress that additionally applies local stress to the semiconductor device.
Abstract translation: 提供半导体器件结构，通过从外部额外施加压应力或拉伸应力来改变半导体层的物理和电特性。 异质结结构的双极半导体器件包括发射极（211），本征基极（212），集电极（213）和绝缘层侧壁。 用于施加应力的基底被选择性地并外延生长以将半导体器件施加局部应力。 基底可以通过自对准外延生长法具有（311）斜率（218）。 半导体器件结构可以包括用于施加另外对半导体器件施加局部应力的应力的绝缘层（215）。
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公开(公告)号：KR1020170133152A
公开(公告)日：2017-12-05
申请号：KR1020160064248
申请日：2016-05-25
Applicant: 전북대학교산학협력단
CPC classification number: H01L21/02502 , H01L21/0242 , H01L21/02505 , H01L21/0254 , H01L33/007
Abstract: 본발명은템플레이트에피기판및 이의제조방법에관한것으로서, 보다상세하게는크랙이발생하지않는동시에잔류응력해소를통해결정결함및 기판의휨 현상을최소화하는효과를나타내는템플레이트에피기판및 이의제조방법에관한것이다.
Abstract translation: 本发明的模板外延基板和作为其涉及一种方法，用于制备，更具体地与模板外延衬底及其制造方法，示出了晶体缺陷的减少翘曲的效果，并在同一时间在基板的裂纹不通过消除残余应力发生 它涉及。
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公开(公告)号：KR100992483B1
公开(公告)日：2010-11-05
申请号：KR1020090013547
申请日：2009-02-18
Applicant: 전북대학교산학협력단
IPC: H01L31/04
CPC classification number: Y02E10/50
Abstract: 본 발명은 쇼트키 접합을 이용한 태양전지 및 이의 제조방법에 관한 것으로, 더욱 상세하게는 실리콘 기판과 금속 실리사이드 전극과의 쇼트키 접합 특성을 나타내는 후면 전극형 태양전지 및 이의 제조방법에 관한 것이다.
상기 후면 전극형 태양전지는 간단한 공정으로 인해 제작비용 절감과 동시에 입사되는 태양광의 광손실을 최소화하여 고효율 태양 전지를 구현한다.
태양전지, 쇼트키 접합-
公开(公告)号：KR1020100115928A
公开(公告)日：2010-10-29
申请号：KR1020090034588
申请日：2009-04-21
Applicant: 전북대학교산학협력단
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/0891 , H01L21/02225 , H01L21/02244 , H01L27/095 , H01L29/41725 , H01L29/42312 , H01L29/4232
Abstract: PURPOSE: The manufacturing method of the Schottky barrier transistor element It relatively facilitates, the high-end having the high action electric current density, and the device of the high quality can be manufactured. CONSTITUTION: The manufacturing method of the Schottky barrier transistor element(1) the gate insulating film layer is formed on the silicon comprising substrate. The gate electrode layer is formed on the isolation film layer front side. The gate insulating film layer and gate electrode layer are etched and the gate insulating layer and gate electrode are formed.
Abstract translation: 目的：肖特基势垒晶体管元件的制造方法相对而言，具有高动作电流密度的高端，能够制造高质量的器件。 构成：在包含硅的衬底上形成肖特基势垒晶体管元件（1）栅极绝缘膜层的制造方法。 栅电极层形成在隔离膜层正面上。 蚀刻栅极绝缘膜层和栅极电极层，形成栅极绝缘层和栅极电极。
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