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公开(公告)号：CA2422221A1
公开(公告)日：2002-03-21
申请号：CA2422221
申请日：2001-09-06
Applicant: IBM
Inventor： WIND DANIEL , ROMAN THIERRY , BLANC ALAIN , GALLEZOT RENE , LE MAUT FRANCOIS , BREZZO BERNARD
IPC: H04L12/18 , H04L49/111 , H04L12/56
Abstract: The invention allows to assess a level of multicast traffic in a data switch of the kind devised to steer fixed-size data packets, from input to output ports, through a shared memory which temporarily holds a single copy of them in buffers. Output ports are each equipped with an output port queue which contains pointers to those of the buffers holding data packets due to leave the data switch through them. Then, the invention assumes that the total number of shared-memory buffers currently holding a data packet is counted a nd compared to the total number of buffer pointers found in the output queues. Hence, a metric of the level of multicast traffic is derived resulting in th e calculation of a MultiCast Index (MCI). The invention further assumes that data switch is used together with a Switch Core Adaptation Layer (SCAL) whic h includes a multicast input queue. Because traffic is handled on the basis of a set of priority classes a multicast threshold MCT(P), associated to the multicast input queue, per priority, is set or updated. Therefore, while receiving incoming data traffic, MCI is kept calculated and, for each priori ty class (P), in each SCAL, MCI is compared to MCT(P) to determine whether corresponding multicast traffic must be held or not. The invention helps preventing traffic congestion in communications networks, using fixed-size data packet switches, that would otherwise occur when a high level of multicast and broadcast traffic has to be supported at network nodes.
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公开(公告)号：DE69027531D1
公开(公告)日：1996-07-25
申请号：DE69027531
申请日：1990-09-28
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , UNGERBOECK GOTTFRIED DR , BLANC ALAIN
Abstract: Data circuit terminating equipment DCE (100) which allows the connection of a Data terminal equipment DTE (63) to a telecommunication line and which includes timing arrangements circuits for particularly providing the DTE with transmitter signal element timing (114) and receiver signal element timing (115). The DCE includes processing means (61) for computing a sequence of digital values A(n) and means (60, 23, 22) for deriving from said sequence of digital values A(n) a corresponding sequence of interrupt signals T(n). The DCE further includes timing arrangement circuits (69, 70, 71) for generating a set of N timing pulses at the nominal rate on the occurrence of one interrupt signal T(n). By controlling the generation of the sequence of digital values, the processing means (61) can control the frequency, the phase of every clock generated by the timing arrangements circuits. The receiver signal element timing, the transmitter signal element timing the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are controlled by different sequence of digital values computed by the processing means. By generating appropriate sequences of digital values, the processing means can provide any relationship between the different clocks: a transmit signal element timing being slaved on the receiver signal element timing in a synchronous mode, on an external clock in a tailing mode. The timing arrangement circuits can also provide a transmit sampling clock slaved on the receive sampling clock in order to perform powerful digital echo cancellation techniques. More generally, the processing means (61) can provide any relationship between two determined clocks. Moreover, the DCE including a DTE receive interface circuit 21 transmitting a set of N receive data at the nominal receive clock rate and maintaining the N data bit until the next interrupt signal, the processing means can control the length of the Nth bit, which when a STOP bit can allow the compensation of the DTE and the line data throughput difference.
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公开(公告)号：DE60317890T2
公开(公告)日：2008-11-27
申请号：DE60317890
申请日：2003-03-31
Applicant: IBM
Inventor： ABEL FRANCOIS G , BENNER ALAN , BLANC ALAIN , COLMANT MICHEL , GUSAT MITCH , PORET MICHEL , SCHUMACHER NORBERT , VERHAPPEN MARK
Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
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公开(公告)号：DE60317890D1
公开(公告)日：2008-01-17
申请号：DE60317890
申请日：2003-03-31
Applicant: IBM
Inventor： ABEL FRANCOIS G , BENNER ALAN , BLANC ALAIN , COLMANT MICHEL , GUSAT MITCH , PORET MICHEL , SCHUMACHER NORBERT , VERHAPPEN MARK
Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
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公开(公告)号：DE69737676T2
公开(公告)日：2008-01-10
申请号：DE69737676
申请日：1997-08-19
Applicant: IBM
Inventor： BLANC ALAIN , SAUREL ALAIN , BREZZO BERNARD , PORET MICHEL
IPC: H04L49/111 , H04Q11/04
Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.
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Patent Agency Ranking
公开(公告)号：DE69734968D1
公开(公告)日：2006-02-02
申请号：DE69734968
申请日：1997-08-19
Applicant: IBM
Inventor： BLANC ALAIN , NICOLAS LAURENT , GOHL SYLVIE
IPC: H04L12/54 , H04L49/111 , H04Q11/04
Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit includes means for introducing at least one extra byte to every cell. The extra byte is reserved for carrying a routing header for controlling the switching structure in a first step, and then for use by the PINT circuit when the cell will be received by the transmit part in a second step. The transmit part of each PINT circuit comprises a control module that receives all the cells generated at the corresponding output port and controls whether to discard the cell based on the value of the extra byte.
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37.发明专利
公开(公告)号：AU2003215841A1
公开(公告)日：2003-11-17
申请号：AU2003215841
申请日：2003-03-31
Applicant: IBM
Inventor： ABEL FRANCOIS G , BENNER ALAN , BLANC ALAIN , COLMANT MICHEL , GUSAT MITCH , PORET MICHEL , SCHUMACHER NORBERT , VERHAPPEN MARK
Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.
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公开(公告)号：DE69223508D1
公开(公告)日：1998-01-22
申请号：DE69223508
申请日：1992-07-10
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
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公开(公告)号：DE69125816D1
公开(公告)日：1997-05-28
申请号：DE69125816
申请日：1991-02-21
Applicant: IBM
Inventor： BLANC ALAIN , GOHL-ROUX SYLVIE , UNGERBOECK GOTTFRIED
Abstract: DCE and method for performing the processing of data into a DCE, and DCE which includes a digital signal processor DSP (202) for processing the data transmitted between a Data terminating equipment DTE (209) and a telecommunication line, transmit (213) and receive (214) circuits being connected to the DTE interface. The DCE further includes A/D (215) and a D/A converters (216) for respectively converting the data from an analog form to Pulse Coded Modulation PCM words and from PCM words to an analog form and also a control processor (200) for controlling the communication protocols and a storage (204) which is connected to both the DSP processor (202) and the control processor (200). The method is characterized in that it involves the steps of storing (403) by means of said DSP processor (202) the bits provided by said transmit circuit (213) into a first queue (300) which is located into said storage (204) and storing (507) into a second queue (304) which is also located into the same storage (204) the characters being computed by said DSP processor (202) and deriving from the bits stored into said first queue (300) accordingly to a first given transmission protocol being either a start-stop, a HDLC or a BSC transmission protocol. The method further involves the step of storing (513) into a third queue (307) which is located into the same storage as above the characters being provided by said control processor (200) in order to be transmitted to a remote DCE via the telecommunication line. A further step is involved which is the storing (513) into a fourth queue (309) which is still located into the storage (204) the bits being computed by said DSP processor (202) and deriving from the characters stored into said third queue (307) accordingly to a second given transmission protocol. the transmission of data through the telecommunication line is achieved by storing into a fifth queue (302) the PCM words which are computed by said DSP processor (202) in accordance with a given modulation algorithm, the PCM words being derived either from the contents of said first (300) queue in synchronous mode or from the contents of the third (307) queue when the transmit part of the DCE is intended to operate in an asynchronous mode or still when the control processor (200) wishes to transmit data through the telecommunication line. The selection of an appropriate transmission protocol, chosen the existing protocols such as start-stop, HDLC, BSC, as well as the selection of the appropriate modulation algorithm provides a method for processing data to be transmitted from a DTE to a telecommunication line which allows a large number of configuration without requiring the great number of electronic components which were usually necessary. The invention also provides the receive part of the DCE.
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公开(公告)号：DE69118372T2
公开(公告)日：1996-11-14
申请号：DE69118372
申请日：1991-07-17
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , BLANC ALAIN , JEANNIOT PATRICK , RICHTER GERARD
Abstract: A Decimation filter for converting a train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples in accordance with the formula The decimation filter comprises means for computing one PCM sample from a sequence of 1 sigma-delta samples in synchronism with a PCM clock. and also means for determining whether a phase correction has to be introduced in said PCM clock in order to lock the generation of the PCM samples on the receive clock extracted from the received signal. From the latter determination, the decimation filter has means (410, 311, 411, 312, 412, 313) which shifts the computation process of the sequence of at least one sigma-delta clock pulse in order to provide a phase control of the generation of the PCM samples. In a preferred embodiment, the value of p is equal to 3 and the filter includes computing means (350, 360, 370) for computing one PCM sample from a sequence of 3xN input samples according to the formula: where C(n) is the sequence of the coefficients of the decimation filter corresponding to a determined decimation factor N. The filter further includes - means (321, 327, 331, 337, 341, 347) for generating the sequence C(n) corresponding to a determined decimation factor N, and multiplying means (323, 333, 343) for multiplying each coefficient C(n) of said sequence by a sigma-delta input sample S(i+n). The filter detects the occurence of the coefficient C(2xN-1) which is equal to zero and includes means (311, 312, 313) responsive to the detection of said coefficient C(2xN-1) for shifting of one sigma-delta clock pulse the initiating of the computing process of the next PCM pulse in order to provide a phase control of the generation of the PCM samples.
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