公开(公告)号：CA2051175C

公开(公告)日：1998-03-31

申请号：CA2051175

申请日：1991-09-11

Applicant: IBM

Inventor： STUTES RODGER M ,  BLAND PATRICK M ,  CROMER DARYL C ,  ALDEREGUIA ALFREDO

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：DE69031768D1

公开(公告)日：1998-01-15

申请号：DE69031768

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：AT160890T

公开(公告)日：1997-12-15

申请号：AT90305297

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：SG42806A1

公开(公告)日：1997-10-17

申请号：SG1995002115

申请日：1990-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA2016400C

公开(公告)日：1996-01-02

申请号：CA2016400

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/16

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：CA2124031A1

公开(公告)日：1994-11-29

申请号：CA2124031

申请日：1994-05-20

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/14

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：CA1319201C

公开(公告)日：1993-06-15

申请号：CA598606

申请日：1989-05-03

Applicant: IBM

Inventor： BLAND PATRICK M ,  DEAN MARK E

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F12/00 ,  G11C8/00 ,  G06F13/16

Abstract: BC9-88-002 A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.

公开(公告)号：BR9103873A

公开(公告)日：1992-06-16

申请号：BR9103873

申请日：1991-09-09

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK M ,  CROMER DARYL C ,  STUTES ROGER M

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F15/20

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：BR9002876A

公开(公告)日：1991-08-20

申请号：BR9002876

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F9/00

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：BR9002554A

公开(公告)日：1991-08-13

申请号：BR9002554

申请日：1990-05-30

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F9/00

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.