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公开(公告)号：DE68916413D1
公开(公告)日：1994-07-28
申请号：DE68916413
申请日：1989-03-14
Applicant: IBM
Inventor： BARUCCHI GERARD , CALVIGNAC JEAN , ORSATTI DANIEL , TRACOL ANDRE
IPC: G06F15/16 , G06F15/167 , G06F15/173
Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.
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公开(公告)号：DE3883528T2
公开(公告)日：1994-03-17
申请号：DE3883528
申请日：1988-06-16
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE LES JARDINS DE CESS , SAINT-GEORGES ERIC
Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.
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公开(公告)号：DE3685217D1
公开(公告)日：1992-06-11
申请号：DE3685217
申请日：1986-08-27
Applicant: IBM
Inventor： CALVIGNAC JEAN , SECONDO PIERRE
Abstract: The bandwidth allocation mechanism comprises a unit (30-T,32-T) for dynamically and instantaneously qualifying the circuit slots, depending upon the user actively detected on a slot basis to set a qualifying bit to a value. The value indicates that the slot is assigned to a boundary circuit user. Another value indicates that the slot is momentarily free and may be assigned to the packet switched traffic. The qualifying bits are transported through the network in correspondence with the slots they qualify. Another unit (30-R,32-R) responds to the received qualifying bits and to the received bits for reconstructing boundary circuit user bit streams. The streams comprise the user data bits when the qualifying bits are found equal to the first value and to idle bit configurations when the qualifying bit is found equal to the second value.
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公开(公告)号：DE3580485D1
公开(公告)日：1990-12-13
申请号：DE3580485
申请日：1985-12-23
Applicant: IBM
Inventor： BOUILLOT MICHEL , CALVIGNAC JEAN , MUNIER JEAN-MARIE LUCIEN
Abstract: Serial link adapter to be used in a communication controller comprising data handling means (DHM), said adapter allowing the communication controller to be attached to a multiplex serial link carrying data and non coded information bits in dedicated slots.In line adapter LA1 receiving means RCV1 are connected to serial link carrying data and non coded information slots. The receiving means comprises a routing arrangement for sending the data slot bits to the data handling means of the controller and the non coded information slot bits a high speed bus HSB1. Transmitting means Xmit1 are connected to high speed bus HSB2 and to the data handling means and comprises means for sending the data and non coded information slot bits in dedicated slots on the serial multiplex link MPX-T. Line adapter LA2 comprises means which are similar to the receiving and transmitting means in adapter LA1 and may be connected to the private branch exchange located in the same site as the communication controller.
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公开(公告)号：DE3580276D1
公开(公告)日：1990-11-29
申请号：DE3580276
申请日：1985-08-13
Applicant: IBM
Inventor： CALVIGNAC JEAN , SECONDO PIERRE
Abstract: Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network.Each complex frame which contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256), is made of a succession of subframes and delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Division Multiplex Frames (125 microseconds) and n being an integer number higher or equal to 1 which depends upon the medium link bit rate and e being a period of time lower than a medium link bit period.The subframes have a duration less or equal to T, each subframe i contain an integer number Nsi of bits, said integer number being allocated to carry an integer number of circuit switched bit slots and the remaining bits being used to carry asynchronous packet switched bits.The R bits remaining in the complex frame, with are used to carry f flag bits and r=R-f padding bits which are used to carry asynchronous packet switched bits.
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Patent Agency Ranking
公开(公告)号：CA1250936A
公开(公告)日：1989-03-07
申请号：CA505862
申请日：1986-04-04
Applicant: IBM
Inventor： CALVIGNAC JEAN , SECONDO PIERRE
Abstract: Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network. Each complex frame which contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256), is made of a succession of subframes and delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Division Multiplex Frames (125 microseconds) and n being an integer number higher or equal to 1 which depends upon the medium link bit rate and e being a period of time lower than a medium link bit period. The subframes have a duration less or equal to T, each subframe i contain an integer number Nsi of bits, said integer number being allocated to carry an integer number of circuit switched bit slots and the remaining bits being used to carry asynchronous packet switched bits. The R bits remaining in the complex frame, with are used to carry f flag bits and r=R-f padding bits which are used to carry asynchronous packet switched bits. Figure 2-A
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公开(公告)号：GB2502455A
公开(公告)日：2013-11-27
申请号：GB201312415
申请日：2011-12-12
Applicant: IBM
Inventor： VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN , ABEL FRANCOIS , CHANG CHIH-JEN , PHILLIPE DAMON
Abstract: The invention provides for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
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公开(公告)号：DE112011104443T5
公开(公告)日：2013-09-12
申请号：DE112011104443
申请日：2011-12-19
Applicant: IBM
Inventor： VERPLANKEN FABRICE JEAN , VERRILLI COLIN , VAIDHYANATHAN NATARAJAN , PHILIPPE DAMON , CHANG CHIH-JEN , CALVIGNAC JEAN , BASSO CLAUDE
IPC: G06F9/38 , G06F15/163 , H04L29/06
Abstract: Das Optimieren der Anzahl von Lanes eines Netzwerkprozessors, wenn ein Anforderungs-/Antwort-Datenverkehr zwischen dem Parser von Netzwerkprozessor-Ethernet-Anschlüsse und einem externen Coprozessor umgesetzt wird, weist bei Empfang eines 64-Byte-Ethernet-Pakets im Ethernet-Anschluss und während der Parsing-Periode auf, dass der Parser eine Anforderung mit einem Wort von 16 Byte an den Coprozessor auf der weiteren (bidirektionalen) 3,125-Lane sendet und als Reaktion darauf ein Wort mit 16 Byte auf der weiteren (bidirektionalen) 3,125-Lane empfängt. Der Coprozessorzugriff-Datenverkehr mit einem Wort von 16 Byte und ein (bidirektionaler) Datenverkehr mit einer Einheit im Netzwerkprozessor können statisch gemultiplext werden, wobei ein oder der andere Datenverkehr eingerichtet wird, wenn der Netzwerkprozessor initialisiert wird. Es wird ein dynamisches Multiplexing des Coprozessorzugriff-Datenverkehrs mit einem Wort von 16 Byte in einem Ethernet-Anschluss und des Coprozessorzugriff-Datenverkehrs mit einem Wort von 16 Byte in einem anderen Ethernet-Anschluss durchgeführt, wobei das dynamische Multiplexing mit einem Umlaufalgorithmus arbitriert wird.
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公开(公告)号：AT384380T
公开(公告)日：2008-02-15
申请号：AT01917224
申请日：2001-03-26
Applicant: IBM
Inventor： BASS BRIAN , CALVIGNAC JEAN , HEDDES MARCO , SIEGEL MICHAEL , VERPLANKEN FABRICE
Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
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公开(公告)号：DE69735608T2
公开(公告)日：2007-04-05
申请号：DE69735608
申请日：1997-04-08
Applicant: IBM
Inventor： CALVIGNAC JEAN , ORSATTI DANIEL , VERPLANKEN FABRICE
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