中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

46 records (took 0.016 seconds)

    MICRO MECHANICAL ACTUAL TRANSDUCER HEAD ON A SLIDER
    32.
    发明专利
    MICRO MECHANICAL ACTUAL TRANSDUCER HEAD ON A SLIDER 未知

    公开(公告)号：CA1275503C

    公开(公告)日：1990-10-23

    申请号：CA532514

    申请日：1987-03-19

    Applicant: IBM

    Inventor： COCKE JOHN ,  KHANNA VIJAYESHWAR D ,  YEACK-SCRANTON CELIA E

    IPC: G11B5/58 ,  G11B5/60 ,  G11B7/09 ,  G11B7/12 ,  G11B21/12 ,  G11B21/20 ,  G11B21/21 ,  G11B33/10 ,  G11B5/54

    Abstract: YO986-013 MICRO MECHANICAL ACTUATED TRANSDUCER HEAD ON A SLIDER A micro-mechanical actuated transducer head on an air bearing slider is disclosed herein. The transducer head is made to move relative to the slider assembly by the incorporation of an actuating material intermediately to the slider assembly and head. The actuating material can be: electromechanical, piezoelectric, electrostrictive, thermal, pneumatic, or hydraulic. The actuating material can be incorporated either integral to the head/slider assembly or made to bridge the slider to head attachment. With the incorporation of said actuatable material, said head can be moved micro-mechanically relative to said slider effecting relative and controllable motion either horizontally and/or vertically.

    33.
    发明专利
    未知

    公开(公告)号：DE3577761D1

    公开(公告)日：1990-06-21

    申请号：DE3577761

    申请日：1985-06-03

    Applicant: IBM

    Inventor： COCKE JOHN ,  HAILPERN BRENT TZION ,  HOEVEL LEE WINDSOR ,  SHAPIRO EUGENE ,  BLOUNT MARION LEE

    IPC: G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/173

    Abstract: A plurality of intelligent work stations (10) are provided access to a shared memory (12) through a switching hierarchy including a first array of mapping boxes (14) for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch (16) for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes (18) for receiving the logical address and offset and for I converting the logical address into a memory switch port designation and physical address, and a second switch (20) for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.

    ERROR CORRECTION ON BURST CHANNELS BY SEQUENTIAL CODING
    35.
    发明专利
    ERROR CORRECTION ON BURST CHANNELS BY SEQUENTIAL CODING 未知

    公开(公告)号：CA1129030A

    公开(公告)日：1982-08-03

    申请号：CA354508

    申请日：1980-06-20

    Applicant: IBM

    Inventor： BAHL LALIT R ,  COCKE JOHN ,  CULLUM CLIFTON D JR ,  HAGENAUER JOACHIM

    IPC: G06F11/10 ,  H03M13/23 ,  H04L1/00 ,  H04L1/10

    Abstract: ERROR CORRECTION ON BURST CHANNELS BY SEQUENTIAL DECODING A sequential decoder for error correction on burst and random noise channels using convolutionally encoded data. The decoder interacts with a deinterleaver which time demultiplexes data from a data channel from its time multiplexed form into a predetermined transformed order. The decoder includes a memory for storing a table of likelihood values which are derived from known error statistics about the data channel such as the probabilities of random errors and burst errors, burst error severity and burst duration. The decoder removes an encoded subblock of data from the deinterleaver and enters it into a replica of the convolutional encoder which calculates a syndrome bit from a combination of the presently received subblock together with a given number of previous subblocks. The syndrome bit indicates if the current assumption of the path through the convolutional tree is correct. Where there is no error in the channel, then the received sequence is a code word and the syndrome bit indicates that the correct path in the convolution tree is taken. For each received bit, an indicator bit is calculated which is a function of the difference between the current path and the received sequence. The sequential decoder employs the syndrome bit together with burst indicator bits to calculate a table address in a table of likelihood values and error pattern values. The likelihood value is used to update a total likelihood of error value and the error pattern value is used to change the received subblock of data. YO975-038

    36.
    发明专利
    未知

    公开(公告)号：DE2001664A1

    公开(公告)日：1970-07-23

    申请号：DE2001664

    申请日：1970-01-15

    Applicant: IBM

    Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  HENRY SUSSENGUTH EDWARD

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/16

    Abstract: 1282341 Data processing INTERNATIONAL BUSINESS MACHINES CORP 12 Jan 1970 [15 Jan 1969] 1358/70 Heading G4A In stored-program data processing apparatus, switching to another instruction stream as a result of a successful conditional branch instruction occurs after execution of a marker instruction. Instructions are accessed from memory and inserted into the top of a multi-instruction pushdown buffer together with bits indicating, for each instruction, whether or not it is a target, branch or exit instruction. The target bit is provided at the memory (see below) and the branch and exit bits are derived by a predecoder. The instruction at the bottom of the buffer is decoded. If it is a branch instruction, two fields in it select two bits from a condition register and 1 of 8 logical functions of these specified by part of the op code is evaluated in a function generator to determine whether the branch should be taken, the branching being to an address obtained by adding a field from the instruction and the contents of one of a plurality of registers selected by another field of the instruction. However, the sequence of instruction fetching branches to this address only when the next exit instruction enters the buffer. The branched-to instruction has its target bit set to 1 at the memory. Decoding and therefore execution of each instruction in the buffer between the exit instruction and the target instruction is inhibited, the inhibition terminating when the target instruction is shifted into the bottom position of the buffer, in response to the target bit of 1. Decoding of any branch instruction after a successful branch instruction and before the next exit instruction is also inhibited. If both an exit and a branch instruction are present in the buffer but a successful branch has not been determined, instruction fetching is suspended until not all these conditions exits, thus awaiting the result of the branch test. Instruction fetching is from the next sequential address if there is no exit instruction in the buffer, and if there is but there is neither a branch instruction in the buffer nor an indication of a successful branch determined.

    METHOD AND SYSTEM FOR NATURAL LANGUAGE TRANSLATION
    37.
    发明专利
    METHOD AND SYSTEM FOR NATURAL LANGUAGE TRANSLATION 未知

    公开(公告)号：CA2068780C

    公开(公告)日：1998-12-22

    申请号：CA2068780

    申请日：1992-05-15

    Applicant: IBM

    Inventor： BROWN PETER F ,  COCKE JOHN ,  DELLA PIETRA STEPHEN A ,  DELLA PIETRA VINCENT J ,  JELINEK FREDERICK ,  LAI JENNIFER C ,  MERCER ROBERT L

    IPC: G10L15/14 ,  G06F17/27 ,  G06F17/28 ,  G10L15/00

    Abstract: The present invention is a system for translating text from a first source language into second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest, scoring translations. The source text is first transduced into one or more intermediate structural representations. From these intermediate source structures a set of intermediate target-structure hypotheses is generated. These hypotheses are scored by two different models: a language model which assigns a probability or score to an intermediate target structure, and a translation model which assigns a probability or score to the event that an intermediate target structure is translated into an intermediate source structure. Scores from the translation model and language model are combined into a combined score for each intermediate target-structure hypothesis. Finally, a set of target-text hypotheses is produced by transducing the highest scoring target-structure hypotheses into portions of text into the target language. The system can either run into batch mode, in which case it translates source-language text into a target language without human assistance, or it can function as an aid to a human translator. When functioning as an aid to a human translator, the human may simply select from the various translation hypotheses provided by the system, or he may optionally provide hints or constraints on how to perform one or more of the states of source transduction, hypothesis generation and target transduction.

    A hierarchical memory system including separate cache memories for storing data and instructions
    39.
    发明专利
    A hierarchical memory system including separate cache memories for storing data and instructions 未知

    公开(公告)号：HK7695A

    公开(公告)日：1995-01-27

    申请号：HK7695

    申请日：1995-01-19

    Applicant: IBM

    Inventor： CARRUBBA FRANK PAUL ,  COCKE JOHN ,  KREITZER NORMAN ,  RADIN GEORGE

    IPC: G06F12/08 ,  G06F12/12

    Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement with the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory. … The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Moditication of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted. … The cache architecture and controls permit normal instruction and data cache fetches and data cache stores. Additionally, special instructions are provided for setting the special control bits provided in both the instruction and data cache directories, independently of actual memory accessing OPS by the CPU and for storing and loading cache lines independently of memory OPS by the CPU.

Patent Agency Ranking