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公开(公告)号：DE60234903D1
公开(公告)日：2010-02-11
申请号：DE60234903
申请日：2002-01-17
Applicant: IBM
Inventor： BARKER KENNETH JAMES , DAVIS GORDON TAYLOR , JEFFRIES CLARK DEBS , RINALDI MARK ANTHONY , SUDEEP KARTIK
Abstract: The decision to discard or forward a packet is made by a flow control mechanism, upstream from the forwarding engine in the node of a communication network. The forwarding engine includes a switch with mechanism to detect congestion in the switch and return a binary signal B indicating congestion or no congestion. The flow control mechanism uses B and other network related information to generate a probability transmission table against which received packets are tested to determine proactively whether a packet is to be discarded or forwarded.
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公开(公告)号：CA2429151C
公开(公告)日：2006-07-25
申请号：CA2429151
申请日：2002-01-17
Applicant: IBM
Inventor： BARKER KENNETH JAMES , DAVIS GORDON TAYLOR , RINALDI MARK ANTHONY , JEFFRIES CLARK DEBS , SUDEEP KARTIK
Abstract: The decision to discard or forward a packet is made by a flow control mechanism, upstream from the forwarding engine in the node of a communicatio n network. The forwarding engine includes a switch with mechanism to detect congestion in the switch and return a binary signal B indicating congestion or no congestion. The flow control mechanism uses B and other network related information to generate a probability transmission table against which received packets are tested to determine proactively whether a packet is to be discarded or forwarded.
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公开(公告)号：DE69633601T2
公开(公告)日：2006-02-02
申请号：DE69633601
申请日：1996-08-09
Applicant: IBM
Inventor： ANDREWS LAWRENCE PAUL , DAVIS GORDON TAYLOR , JOHNSON WILLIE JAMES , JONES JR , LANDA ROBERT EUGENE , MANDALIA BAIJU DHIRAJLAL , SINIBALDI JOHN CLAUDE
Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.
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公开(公告)号：AT280411T
公开(公告)日：2004-11-15
申请号：AT00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：AU2003224007A1
公开(公告)日：2003-10-08
申请号：AU2003224007
申请日：2003-03-10
Applicant: IBM
Inventor： ELEFTHERIOU EVANGELOS S , OELCER SEDAT , ABDELILAH YOUSSEF , DAVIS GORDON TAYLOR , DERBY JEFF H , HWANG DONGMING , WARE MALCOLM , YE HUA
Abstract: A method and systems for optimizing Asymmetric Digital Subscriber Line (ADSL) connections in DSL Access Multiplexor (DSLAM) that marries benefits of G.dmt and G.lite standards, using a flexible method implemented on a programmable Digital Signal Processor (DSP) and a Network Processor (NP) is disclosed. It provides a means to support full G.dmt rates for any of the attached users as long as less than half the users are actively moving data through the DSLAM, but by only using half the digital signal processing hardware and half the power consumption for the line drivers. The invention allows doubling the number of,ADSL ports available over a conventional scheme given about 20% more power is under 50% with only half the respective connections, all those G.dmt rates possible on their exceeds 50%, gradually active G.lite rates based on either based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates. budget. When the utilization subscribers active on their users experience the maximum wire. However, when utilization subscribers start to experience a fixed policy or one that is based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates.
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公开(公告)号：GB2365666A
公开(公告)日：2002-02-20
申请号：GB0107870
申请日：2001-03-28
Applicant: IBM
Abstract: A method and system for testing a plurality of filter rules in a computer system is disclosed. The plurality of filter rules are used with a key that is capable of matching at least one of the plurality of filter rules. The at least one filter rule corresponds to at least one action. The computer system has a cache including a plurality of bins and a decision tree. The method and system include searching a plurality of stored keys in the cache for the key. Preferably, this search of the cache for the key includes determining whether a stored key exactly matches the key. A plurality of stored filter rules corresponds to the plurality of stored keys. A plurality of stored actions corresponds to the plurality of stored filter rules. The cache stores each of the plurality of stored keys and at least one stored action in each bin of a portion of the bins. The method and system also include obtaining the at least one action from the cache if the key is found in plurality of stored keys and otherwise obtaining the at least one action using the decision tree. Preferably, searches of the decision tree and cache start simultaneously. The decision tree search is terminated if the key is found in the cache. The cache is written to if the at least one action is obtained using the decision tree, but preferably only if the at least one filter rule has a priority of one.
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公开(公告)号：CA2334393A1
公开(公告)日：2001-10-04
申请号：CA2334393
申请日：2001-02-02
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , VERPLANKEN FABRICE JEAN , LEAVENS ROSS BOYD , HEDDES MARCO C
Abstract: A prefetch buffer is used in connection with a plurality of independent thre ad processes in such a manner as to avoid an immediate stall when execution is given to an idle thread. A mechanism is established to control the switching from one thread to another within a Processor in order to achieve more efficient utilization of processor resources. This mechanism will grant temporary control to an alternate execution thread when a short latency even t is encountered, and will grant full control to an alternate execution thread when a long latency event is encountered. This thread control mechanism comprises a priority FIFO, which is configured such that its outputs control execution priority for two or more execution threads within a processor, based on the length of time each execution thread has been resident within the FIFO. The FIFO is loaded with an execution thread number each time a new task (a networking packet requiring classification and routing within a network) is dispatched for processing, where the execution thread number loaded into the FIFO corresponds to the thread number which is assigned to process the task. When a particular execution thread completes processing of a particular task, and enqueues the results for subsequent handling, the priority FIFO is further controlled toremove the corresponding execution thread number from the FIFO. When an active execution thread encounters a lo ng latency event, the corresponding thread number within the FIFO is removed from a high priority position in the FIFO, and placed into the lowest priority position of the FIFO. This thread control mechanism also comprises a Thread Control State Machine for each execution thread supported by the processor. The Thread Control State Machine further comprises four states. A n Init state is used while an execution thread is waiting for a task to process. Once a task is enqueued for processing, a Ready state is used to request execution cycles. Once access to the processor is granted, an Execute state is used to support actual processor execution. Requests for additional processor cycles are made from both the Ready state and the Execute state. The state machine is returned to the Init state once processing has been completed for the assigned task. A Wait state is used to suspend requests for execution cycles while the execution thread is stalled due to either a long-latency event or a short-latency event. This thread control mechanism further comprises an arbiter which uses thread numbers from the priority FIFO to determine which execution thread should be granted access to processor resources. The arbiter further process es requests for execution control from each execution thread, and selects one execution thre ad to be granted access to processor resources for each processor execution cycle by matching thread numbers from requesting execution threads with corresponding thread numbers in the priori ty FIFO.
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公开(公告)号：AU2016601A
公开(公告)日：2001-07-16
申请号：AU2016601
申请日：2000-12-21
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：DE68922444D1
公开(公告)日：1995-06-08
申请号：DE68922444
申请日：1989-07-14
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HO LUNG MICHAEL GEORGE , MANDALIA BAIJU DHIRAJLAL , MILLAS ROLAN JOSE , ORTEGA OSCAR EMILIO , PICON RAFAEL JOSE , QUEEN LORAN RAY , ROBINSON RICHARD HOUSTON , ROBINSON WILLIAM ROBERT , SHARP LEO ALVIN , VAN DEN BERG JAN WOUTER
Abstract: A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the host processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.)
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