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公开(公告)号：FI891785A
公开(公告)日：1989-11-27
申请号：FI891785
申请日：1989-04-14
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.
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公开(公告)号：IT8920648D0
公开(公告)日：1989-05-25
申请号：IT2064889
申请日：1989-05-25
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.
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公开(公告)号：IT8920626D0
公开(公告)日：1989-05-24
申请号：IT2062689
申请日：1989-05-24
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , MILLING PHILLIP ERNA
IPC: G06F9/44 , G06F9/445 , G06F13/36 , G06F13/362
Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.
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公开(公告)号：DK189889D0
公开(公告)日：1989-04-19
申请号：DK189889
申请日：1989-04-19
Applicant: IBM
Inventor： BEGUN RALPH MURRAY , BLAND PATRICK MAURICE , DEAN MARK EDWARD
Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.
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公开(公告)号：DE3278982D1
公开(公告)日：1988-10-06
申请号：DE3278982
申请日：1982-06-29
Applicant: IBM
Inventor： DEAN MARK EDWARD , KUMMER DAVID ALLEN , SAENZ JESUS ANDRES
Abstract: A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0°, 180°, 90°, 270°, 135° and 315°, respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F. modulation, with a conventional television receiver. Brighter versions of the colors are obtained by increasing the direct current level (+INTENSITY) at the summing circuit.
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Patent Agency Ranking
公开(公告)号：ZA8500183B
公开(公告)日：1985-11-27
申请号：ZA8500183
申请日：1985-01-08
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
CPC classification number: G06F13/285
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公开(公告)号：AU3409984A
公开(公告)日：1985-07-04
申请号：AU3409984
申请日：1984-10-10
Applicant: IBM
Inventor： DEAN MARK EDWARD , MOELLER DENNIS LEE
Abstract: In a data processing system including a main processor (1) and a co-processor (2), a logic circuit (6) is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honour the interrupt before executing another co-processor instruction.
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公开(公告)号：AT232313T
公开(公告)日：2003-02-15
申请号：AT99973434
申请日：1999-11-30
Applicant: IBM
Inventor： CARPENTER GARY DALE , DEBACKER PHILIPPE LOUIS , DEAN MARK EDWARD , GLASCO DAVID BRIAN , ROCKHOLD RONALD LYNN
IPC: G06F15/173 , G06F9/48 , G06F9/46
Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.
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公开(公告)号：CZ20012153A3
公开(公告)日：2001-09-12
申请号：CZ20012153
申请日：1999-12-10
Applicant: IBM
Inventor： BAUMGARTNER YOANNA , DEAN MARK EDWARD , ELMAN ANNA
Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
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公开(公告)号：AU1397600A
公开(公告)日：2000-07-03
申请号：AU1397600
申请日：1999-11-30
Applicant: IBM
IPC: G06F15/173 , G06F9/48 , G06F9/46
Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.
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