公开(公告)号：AU5216990A

公开(公告)日：1990-11-01

申请号：AU5216990

申请日：1990-03-26

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE3567320D1

公开(公告)日：1989-02-09

申请号：DE3567320

申请日：1985-06-13

Applicant: IBM

Inventor： FANG FRANK FU ,  GROSSMAN BERTRAND M ,  HWANG WEI

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/00

Abstract: A semiconductor device, particularly an ultra-short gate MOSFET, is formed by depositing a mask (6) at a low angle with respect to a planar surface and then performing an angular conductivity conversion operation, such as ion implantation, so that the converted region extends (9) partially under the mask. The mask is then removed and a gate electrode (12) is deposited in its place, the gate being smaller than the channel length (11) from the source (7) to the point (9) where the conversion extended under the mask. Straggle location change is accommodated by arranging that the mask has a dimension along a line parallel to the planar surface which is greater than the desired channel length.

公开(公告)号：AU2003278339A1

公开(公告)日：2004-05-25

申请号：AU2003278339

申请日：2003-10-24

Applicant: IBM

Inventor： HWANG WEI ,  WU KUN

IPC: G06F7/02

Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

公开(公告)号：DE69227432D1

公开(公告)日：1998-12-03

申请号：DE69227432

申请日：1992-08-01

Applicant: IBM

Inventor： DHONG SANG H ,  SHIN HYUN J ,  HWANG WEI

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  H01L21/822 ,  H01L27/04

Abstract: A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage VBST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage VDD. Said voltage regulator comprising: means for generating a reference voltage VREF; first differential means (33) for producing a transition voltage VX from said reference voltage VREF and said power supply voltage VDD, said transition voltage being representative of a fluctuation in said power supply voltage; first transistor means (QP3) for comparing said power supply voltage VDD with said boost voltage VBST; second transistor (QP5) means for comparing said transition voltage VX with said reference voltage VREF; and a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: VBST = - VREF + VDD - VX.

公开(公告)号：DE69126253D1

公开(公告)日：1997-07-03

申请号：DE69126253

申请日：1991-03-21

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI

IPC: G11C11/401 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  G11C8/00

公开(公告)号：DE69027705T2

公开(公告)日：1997-01-23

申请号：DE69027705

申请日：1990-03-29

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE69027705D1

公开(公告)日：1996-08-14

申请号：DE69027705

申请日：1990-03-29

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE68925308D1

公开(公告)日：1996-02-15

申请号：DE68925308

申请日：1989-05-17

Applicant: IBM

Inventor： DAVARI BIJAN ,  HWANG WEI ,  LU NICKY C

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/08 ,  H01L21/82

公开(公告)号：CA2000995C

公开(公告)日：1994-11-08

申请号：CA2000995

申请日：1989-10-20

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  H03K6/02 ,  H03K19/096

Abstract: Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the third node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE3885185D1

公开(公告)日：1993-12-02

申请号：DE3885185

申请日：1988-06-16

Applicant: IBM

Inventor： HWANG WEI ,  LU CHAU-CHUN NICKY

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82 ,  H01L21/205

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.