公开(公告)号：DE10062570C1

公开(公告)日：2002-06-13

申请号：DE10062570

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR

IPC: G11C8/12 ,  G11C11/15 ,  G11C11/14

Abstract: The read and write control circuit has selection transistors provided for each bit line (BL) on both sides of each memory cell connected to respective pairs of read/write amplifiers (AMPH,AMPL) at the bit line ends, each having a current source and a current drain. The read/write amplifiers respond to a write signal, to provide a write current in one or other direction for write-in of a logic 0 or 1 for all bit lines selected by a column select signal applied to a column select line (CS), with read out of the logic 0 or 1 by application of a read signal to a selected memory cell. An Independent claim for a magnetoresistive memory is also included.

公开(公告)号：DE10055936A1

公开(公告)日：2002-05-23

申请号：DE10055936

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14 ,  G11C11/15

Abstract: The device has magnetic memory cells at intersections of a cell field with a matrix of row and column lines. In a write operation the magnetic fields generated by write currents in the lines add at an optional intersection to enable demagnetization of the local memory cell. The shape of the lines is optimized so that the magnetic field component in the plane of the cell field decreases rapidly with increasing distance from the intersection.

公开(公告)号：DE10045042C1

公开(公告)日：2002-05-23

申请号：DE10045042

申请日：2000-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: Single memory cell fields from memory arrays (A) and peripheral circuits (P) assigned to these are interlaced into each other so that utilizing free corner surfaces in a cross-shaped structure produces a high packing density for a module structure. Rows (1-3) in an MRAM module structure are offset to each other so that in row 2, for example, the peripheral circuits bordering on rows 1 and 3 fit in exactly to the corner surfaces of the memory cell fields in rows 1 and 3.

公开(公告)号：DE10032272C2

公开(公告)日：2002-08-29

申请号：DE10032272

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A bit line (BL) first driver (FD) (T1) has an FD current source (J3) and an FD n-channel field effect transistor (N6) with a channel width (wn). The FD current source and the FD field effect transistor connect in series between a BL source of voltage supply (V-SupplyBL) and the BL. A second driver (SD) (T2) for a word line (WL) has an SD current source (J0) that connects with an SD field effect transistor (N0) in series between a WL source of voltage supply (V-SupplyWL) and the WL.

公开(公告)号：DE10041378C1

公开(公告)日：2002-05-16

申请号：DE10041378

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  GOGL DIETMAR

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  H01L27/10

Abstract: A magnetoresistive RAM has many tunneling magnetoresistive memory cells in an array and connected to bitlines and wordlines at respective ends. The other cell ends from the bitlines are joined in at least two groups (1 to 4 or 5 to 8) to a switching transistor (TR1,2) whose gate connects to the corresponding wordline.

公开(公告)号：DE10051173A1

公开(公告)日：2002-04-25

申请号：DE10051173

申请日：2000-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/15

Abstract: Both ends of a selected word line (WL2) are set at a high voltage (V2) to keep the voltage drop on the selected word line as low as possible. A cell (Z22) is read out at an intersecting point between the selected word line and a bit line. Other word lines are set at another voltage level. An Independent claim is also included for a method for reducing the voltage drop along a word/bit line in an MRAM memory.

公开(公告)号：DE10041375A1

公开(公告)日：2002-03-21

申请号：DE10041375

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MUELLER GERHARD ,  GOGL DIETMAR ,  KANDOLF HELMUT

IPC: G11C11/15 ,  G11C17/16 ,  G11C29/00

Abstract: The arrangement includes several memory location fields (1-4) that are provided in a stack one above the other. Each memory location field has redundant memory locations which are provided in the boundary areas (5-8). The addresses of the memory locations to be replaced, are written in the memory cells provided in the boundary areas (9-12) of the memory location fields.

公开(公告)号：DE10034083C1

公开(公告)日：2002-03-14

申请号：DE10034083

申请日：2000-07-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10 ,  H01L23/528

Abstract: A memory matrix based on at least one cell array of column lines and row lines in which at least two column- or row-lines change their location relative to one another i.e. they cross-over one another. The memory matrix has cell arrays stacked in layers one above the other, and in which in each case the column- or row-lines of different layers lie mainly mutually adjacent, opposite one another.

公开(公告)号：DE10037976A1

公开(公告)日：2002-02-21

申请号：DE10037976

申请日：2000-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line

公开(公告)号：DE10032272A1

公开(公告)日：2002-01-24

申请号：DE10032272

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A bit line (BL) first driver (FD) (T1) has an FD current source (J3) and an FD n-channel field effect transistor (N6) with a channel width (wn). The FD current source and the FD field effect transistor connect in series between a BL source of voltage supply (V-SupplyBL) and the BL. A second driver (SD) (T2) for a word line (WL) has an SD current source (J0) that connects with an SD field effect transistor (N0) in series between a WL source of voltage supply (V-SupplyWL) and the WL.