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    MODULO DE CABLEADO TRI-DIMENSIONAL TERMO-FORMADO.
    33.
    发明专利
    MODULO DE CABLEADO TRI-DIMENSIONAL TERMO-FORMADO. 未知

    公开(公告)号：MX9600738A

    公开(公告)日：1997-01-31

    申请号：MX9600738

    申请日：1996-02-26

    Applicant: IBM

    Inventor： NARAYAN CHANDRASEKHAR ,  SHAW JANE M

    IPC: H05K3/46 ,  H05K1/00 ,  H05K3/00 ,  H05K07/02

    Abstract: La presente invencion proporciona un modulo de cableado que contiene una pluralidad de capas de polímero laminado, que contiene un grupo de circuitos electronicos definido, que puede termoformarse en formas tridimensionales deseadas sin dañar el cableado interno en la region de tension de termoformado. Más particularmente, la invencion proporciona un modulo de cableado tridimensional termoformado que se prepara al termoformar un laminado que comprende una pluralidad de capas aislantes de polímero termoformables, laminadas que contienen circuitos de cableado conductores cuando menos en una superficie de las capas, las capas están ensambladas para formar trayectorias de interconexion conductoras dentro del modulo, el modulo además está caracterizado porque los circuitos de cableado conductores están presentes solo en capas de baja tension internas de laminado en la region de doblez de termoformado presente en el modulo.

    34.
    发明专利
    未知

    公开(公告)号：DE60307793D1

    公开(公告)日：2006-10-05

    申请号：DE60307793

    申请日：2003-02-27

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： IYER S SUNDAR K ,  IYER SUBRAMANIAN S ,  KOTHANDARAMAN CHANDRASEKHARAN ,  NARAYAN CHANDRASEKHAR

    IPC: H01L23/525

    Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.

    36.
    发明专利
    未知

    公开(公告)号：DE60034611T2

    公开(公告)日：2008-01-31

    申请号：DE60034611

    申请日：2000-02-04

    Applicant: QIMONDA AG ,  IBM

    Inventor： WEBER STEFAN J ,  IGGULDEN ROY ,  NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL CHRISTOPH ,  HOINKIS MARK ,  VAN DEN BERG ROBERT

    IPC: H01H85/00 ,  H01H69/02 ,  H01L23/525 ,  H01L21/82

    Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

    Partially non-volatile dynamic random access memory
    37.
    发明专利
    Partially non-volatile dynamic random access memory 未知

    公开(公告)号：GB2355327A

    公开(公告)日：2001-04-18

    申请号：GB0017095

    申请日：2000-07-13

    Applicant: IBM

    Inventor： KIRIHATA TOSHIAKI ,  STORASKA DANIEL ,  NARAYAN CHANDRASEKHAR ,  TONTI WILLIAM ,  BERTIN CLAUDE ,  VAN HEEL NICK

    IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112

    Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip. Each cell includes a capacitor which permanently stores a 1 by breakdown of the capacitor when the cell acts as an EPROM cell.

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