公开(公告)号：DE102005001668A1

公开(公告)日：2006-03-16

申请号：DE102005001668

申请日：2005-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HAPP THOMAS

IPC: G11C16/00 ,  G11C11/4099

Abstract: The circuit has a phase-changeable memory cell (1) with phase changeable material. An evaluating processor unit has a comparator that compares an electrical value that is dependant on a resistance value of the material with a reference value and determines the condition of the cell based on the comparison result. A reference value unit is designed to generate the reference value dependent on temperature of the material.

公开(公告)号：DE102004040750A1

公开(公告)日：2006-03-09

申请号：DE102004040750

申请日：2004-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  SYMANCZYK RALF ,  KUND MICHAEL

IPC: G11C7/00 ,  G11C13/00

Abstract: A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.

公开(公告)号：DE102004040752A1

公开(公告)日：2006-03-02

申请号：DE102004040752

申请日：2004-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G11C11/00 ,  H01L21/8239 ,  H01L27/24

Abstract: An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method.

公开(公告)号：DE102005014508A1

公开(公告)日：2005-10-20

申请号：DE102005014508

申请日：2005-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  ROEHR THOMAS

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G9/22 ,  H01L23/525 ,  H01L27/24

公开(公告)号：DE50000970D1

公开(公告)日：2003-01-30

申请号：DE50000970

申请日：2000-03-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C7/14 ,  G11C11/22

Abstract: An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

公开(公告)号：DE59902239D1

公开(公告)日：2002-09-05

申请号：DE59902239

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NEUHOLD ERNST ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  BOEHM THOMAS ,  ROEHR THOMAS

IPC: G11C11/22 ,  G06F11/20 ,  G11C29/00 ,  G11C29/04

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

公开(公告)号：DE10102432A1

公开(公告)日：2002-08-08

申请号：DE10102432

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JACOB MICHAEL ,  ROEHR THOMAS

IPC: G11C29/12 ,  G11C29/40 ,  G11C11/22

公开(公告)号：DE10102430A1

公开(公告)日：2002-08-08

申请号：DE10102430

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JACOB MICHAEL ,  ROEHR THOMAS

IPC: G11C29/34 ,  G11C29/50 ,  G11C11/22

Abstract: The circuit (1a) is in the form of a digital circuit integrated into the ferroelectric memory component and is designed to write to several ferroelectric memory cells (Z) simultaneously in test mode, whereby read amplifiers (LV1,LV2) used in normal mode are deactivated or isolated from bit lines (BL1,..) of a cell field of the ferroelectric memory component by electronic switches. Independent claims are also included for the following: a ferroelectric memory component.

公开(公告)号：DE60305668T2

公开(公告)日：2007-05-16

申请号：DE60305668

申请日：2003-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOACHIM HANS-OLIVER ,  ROEHR THOMAS

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12 ,  G11C11/22

Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, -0.5 to -1.0V. This increases the effective plateline pulse (V PLH ) to V PLH +the magnitude of the negative voltage. This results in an increase in the difference between V HI and V L0 read signals, thereby increasing the sensing window.

公开(公告)号：DE102004045219A1

公开(公告)日：2006-03-30

申请号：DE102004045219

申请日：2004-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS

IPC: G11C7/14

Abstract: A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage difference in a measuring device, in particular, a differential sense amplifier.