公开(公告)号：DE59808351D1

公开(公告)日：2003-06-18

申请号：DE59808351

申请日：1998-09-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTENSCHLAGER RAINER ,  SCHNEIDER RALF ,  SICHERT CHRISTIAN ,  MANYOKI ZOLTAN

IPC: H03K17/12 ,  H03K17/16 ,  H03K19/003

Abstract: A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.

公开(公告)号：DE10058324A1

公开(公告)日：2002-06-13

申请号：DE10058324

申请日：2000-11-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  BENZINGER HERBERT

IPC: G11C7/10 ,  G11C7/22

公开(公告)号：DE10014386A1

公开(公告)日：2001-09-27

申请号：DE10014386

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  SCHROEDER STEPHAN

IPC: G01R31/317 ,  G01R31/3185 ,  H03K5/22 ,  G11C11/407

Abstract: The integrated circuit includes a terminal (10) for a digital signal (DQS). A controllable driver circuit (2) has an input (21) to which the terminal (10) is connected, and an output (22) for outputting a digital signal (DQS). A control circuit (3) has an input (31) for a clock signal (CK) for controlling the driver circuit based on the clock signal. A comparator (4) has a first input (41) for the clock signal and a second input (42) which is connected to the output of the driver circuit. The output (A) signal from the comparator has a first state if a signal transition of the signal (CK) at the first input happens before a signal transition of the signal at the second input, and a second state if the transition happens after that at the first input.

公开(公告)号：DE102006017546A1

公开(公告)日：2007-10-18

申请号：DE102006017546

申请日：2006-04-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VERSEN MARTIN ,  SCHNEIDER RALF ,  ZIELBAUER JUERGEN

IPC: G11C29/40

Abstract: A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address of a memory cell lies in a predetermined address space. A controllable unit for storing test results is connected with the test memory and the address comparing unit. The controllable unit is controlled by the address comparing unit such that error information of the tested memory cell is only stored in the test memory if the address of the tested memory cell lies in the selected address space.

公开(公告)号：DE102005014723B4

公开(公告)日：2007-01-18

申请号：DE102005014723

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  KRACH MARKUS ,  VOLLRATH JOERG ,  DUMITRAS GHEORGHE

IPC: G11C11/4072 ,  G11C7/02 ,  G11C11/4074

Abstract: The device (100) includes a reference signal port (203) connected to a signal blocking unit (102) for blocking unwanted signals and to ensure that only a predetermined reference signal (204) is supplied to the electronic switching units (101a-101c). A power supply port (201) applies supply voltage (202) to the electronic switching units. An input signal port (205) supplies an input signal (206) to the electronic switching units. An output signal port (207) is provided to output an output signal (208) after supplying input signal and reference signal to the electronic switching units. An independent claim is included for the initialization process of the electronic switching device.

公开(公告)号：DE102004022425B4

公开(公告)日：2006-12-28

申请号：DE102004022425

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  SCHROEDER STEPHAN

IPC: G05F1/595 ,  G11C5/14 ,  G11C7/00 ,  G11C11/4074

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T 1 ) and a second branch including a charge pump ( 10 ) and a second controllable resistance (T 2 ) are connected between the input terminal (IN) and the output terminal (A). A control circuit ( 20 ) alters the resistance values of the first and second controllable resistances (T 1 , T 2 ) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

公开(公告)号：DE102005014723A1

公开(公告)日：2006-10-05

申请号：DE102005014723

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  KRACH MARKUS ,  VOLLRATH JOERG ,  DUMITRAS GHEORGHE

IPC: G11C11/4072 ,  G11C7/02 ,  G11C11/4074

Abstract: The device (100) includes a reference signal port (203) connected to a signal blocking unit (102) for blocking unwanted signals and to ensure that only a predetermined reference signal (204) is supplied to the electronic switching units (101a-101c). A power supply port (201) applies supply voltage (202) to the electronic switching units. An input signal port (205) supplies an input signal (206) to the electronic switching units. An output signal port (207) is provided to output an output signal (208) after supplying input signal and reference signal to the electronic switching units. An independent claim is included for the initialization process of the electronic switching device.

公开(公告)号：DE102004015269A1

公开(公告)日：2005-11-03

申请号：DE102004015269

申请日：2004-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  CAMPENHAUSEN AUREL VON

IPC: G01R19/165 ,  G11C5/14 ,  G11C11/4074 ,  G11C29/00 ,  G11C29/48 ,  G11C29/50 ,  H02H3/00

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

公开(公告)号：DE10317364B4

公开(公告)日：2005-04-21

申请号：DE10317364

申请日：2003-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  EGGERS GEORG

IPC: G11C8/02 ,  G11C11/406 ,  G11C5/02 ,  G11C8/10

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

公开(公告)号：DE10317364A1

公开(公告)日：2004-11-18

申请号：DE10317364

申请日：2003-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  EGGERS GEORG

IPC: G11C8/02 ,  G11C11/406 ,  G11C5/02 ,  G11C8/10

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.