公开(公告)号：DE10208249B4

公开(公告)日：2006-09-14

申请号：DE10208249

申请日：2002-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/02

公开(公告)号：DE102004029200A1

公开(公告)日：2006-01-12

申请号：DE102004029200

申请日：2004-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DICKMANN RORY ,  SOMMER MICHAEL

IPC: H01L21/60 ,  H01L23/50 ,  H01L23/58 ,  H05K1/16 ,  H05K3/46

Abstract: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.

公开(公告)号：DE10322882A1

公开(公告)日：2004-08-05

申请号：DE10322882

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/407

Abstract: Dynamic memory cell (1) is fitted on word line (WL) and bit line (BL1). Read-out amplifier (3) is coupled to first supply line (12) for high supply potential and second supply line (13) for first low supply potential to amplify charge difference on two bit lines (BL1,2). Two data lines (17) are connectable, via circuit (5) to both bit lines to write datum, by activating this circuit (5), according to two data signals (LDQ1,2) to both bit lines. Control (L1) separates both supply line from supply potentials, with connecting circuit activation, to deactivate amplifier. Independent claims are included for method to write data signal into memory cell.

公开(公告)号：DE10300687A1

公开(公告)日：2004-07-22

申请号：DE10300687

申请日：2003-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L27/092 ,  G11C11/404

Abstract: The substrate contacts of active components lie directly proximate an edge (G) defining adjoining wells (11,12) of different conductivity types. The other structures of the active components lie further away from this edge. The circuit/layout structures of the semiconductor circuit are not mirror symmetrical about the center line (M) of the semiconductor circuit chip (10). Independent claims are included for a DRAM semiconductor circuit, and for a method of manufacturing an integrated semiconductor circuit.

公开(公告)号：DE10260769A1

公开(公告)日：2004-07-15

申请号：DE10260769

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

Abstract: A memory cell comprises a trench capacitor in the base of a trench hole having inner and outer electrodes (9,11) and a dielectric layer (10). A vertical select transistor (TR) has a channel in the upper part of the hole, connecting a capacitor electrode to a bit line (BL), which is completely enclosed by part of the corresponding word line (WL). Independent claims are also included for the following: (a) a memory cell arrangement comprising the above;and (b) a production process for the above

公开(公告)号：DE10214103A1

公开(公告)日：2003-10-23

申请号：DE10214103

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL JOACHIM ,  SOMMER MICHAEL

IPC: G11C11/406 ,  H03K3/0231 ,  H03K3/017

Abstract: The device has a source for providing a current with a predetermined temperature-independent current magnitude, a source for providing a predetermined temperature-independent potential, a source for providing a temperature-dependent reference potential, a capacitor connected to the current source and voltage source for charging and a comparator that outputs a refresh signal if the capacitor voltage exceeds the reference potential. The device has a temperature-independent current source (13) for providing a current with a predetermined temperature-independent current magnitude, a temperature-independent voltage source (14) for providing a predetermined temperature-independent potential, a temperature-dependent reference voltage source (16) for providing a temperature-dependent reference potential, a capacitor (C) connected to the current source and voltage source for charging and a comparator (12) that outputs a refresh signal if the capacitor voltage exceeds the reference potential. AN Independent claim is also included for the following: a method of generating a refresh signal for a memory cell of a semiconducting memory device.

公开(公告)号：DE10051936A1

公开(公告)日：2002-06-06

申请号：DE10051936

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARX THILO ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  HEIN THOMAS ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  HEYNE PATRICK ,  SOMMER MICHAEL

IPC: H02M3/07

公开(公告)号：DE10052211A1

公开(公告)日：2002-05-08

申请号：DE10052211

申请日：2000-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  SOMMER MICHAEL ,  MARX THILO ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  HEIN THOMAS ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

IPC: G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/34 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: A parallel arrangement tests integrated circuits especially DDR SDRAM memory chips. An input connection (10) to one channel of an automatic test unit is linked to a circuit (30), through which the output driver can be switched off in response to an input (10) control signal. The circuit has especially a demultiplexer (31) and a multiplexer (32).In addition to the test control signal (TMCOMP) the demultiplexer can also be controlled by a TMRDS test signal. The input connector (10) is already linked to a test channel, dispensing with the prior art requirement for additional external connections.

公开(公告)号：DE102018126323A1

公开(公告)日：2020-04-23

申请号：DE102018126323

申请日：2018-10-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  OTTERSTEDT JAN

IPC: G11C29/24

Abstract: Gemäß einer Ausführungsform wird eine Speicheranordnung beschrieben aufweisend einen Speicher mit einer Vielzahl von Speicherbereichen und einer Vielzahl von Redundanz-Speicherbereichen und eine Speichersteuereinrichtung, die eingerichtet ist, den Inhalt eines Speicherbereichs zumindest teilweise in einen Redundanz-Speicherbereich auszulagern und den Speicherbereich in einen Speicherzustand zu versetzen, der anzeigt, dass der Inhalt des Speicherbereichs zumindest teilweise in einen Redundanz-Speicherbereich ausgelagert ist.

公开(公告)号：DE102016223568B3

公开(公告)日：2018-04-26

申请号：DE102016223568

申请日：2016-11-28

Applicant: INFINEON TECHNOLOGIES AG ,  PMDTECHNOLOGIES AG

Inventor： PRIMA JENS ,  SOMMER MICHAEL ,  PARASCANDOLA STEFANO ,  OFFENBERG DIRK ,  FEICK HENNING ,  FRANKE MATTHIAS ,  RÖSSLER ROBERT

IPC: H01L27/146 ,  G01S7/481 ,  G01S17/00

Abstract: Eine optische Sensoreinrichtung zum Detektieren einer Laufzeit eines elektromagnetischen Signals umfasst ein Halbleitersubstrat mit einem Umwandlungsgebiet zum Umwandeln von zumindest einem Teil des elektromagnetischen Signals in photoerzeugte Ladungsträger. Eine tiefe Steuerelektrode wird in einem Graben, der sich in das Halbleitersubstrat erstreckt, ausgebildet. Die tiefe Steuerelektrode erstreckt sich tiefer in das Halbleitersubstrat als eine flache Steuerelektrode. Eine Steuerschaltung ist konfiguriert zum Anlegen von variierenden Potenzialen, die eine feste Phasenbeziehung zueinander aufweisen, an die tiefe Steuerelektrode und die flache Steuerelektrode, um elektrische Potenzialverteilungen im Umwandlungsgebiet zu erzeugen, durch die die photoerzeugten Ladungsträger im Umwandlungsgebiet gelenkt werden. Die gelenkten Ladungsträger werden an mindestens einem Ausleseknoten detektiert.