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    31.
    发明专利
    未知

    公开(公告)号：DE19581873C2

    公开(公告)日：1999-04-15

    申请号：DE19581873

    申请日：1995-12-01

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    A MICROPROCESSOR HAVING A MULTIPLY OPERATION
    32.
    发明专利
    A MICROPROCESSOR HAVING A MULTIPLY OPERATION 未知

    公开(公告)号：HK1003189A1

    公开(公告)日：1998-10-16

    申请号：HK98102178

    申请日：1998-03-16

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F5/00 ,  G06F9/305 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F

    Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    Cache hierarchy management with locality hints for different cache levels
    33.
    发明专利
    Cache hierarchy management with locality hints for different cache levels 未知

    公开(公告)号：AU5694098A

    公开(公告)日：1998-07-15

    申请号：AU5694098

    申请日：1997-12-12

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND

    IPC: G06F12/08 ,  G06F13/00

    Abstract: A computer system and method in which allocation of a cache memory is managed by utilizing a locality hint value included within an instruction. When a processor accesses a memory for transfer of data between the processor and the memory, that access can be allocated or not allocated in the cache memory. The locality hint included within the instruction controls if the cache allocation is to be made. When a plurality of cache memories are present, they are arranged into a cache hierarchy and a locality value is assigned to each level of the cache hierarchy where allocation control is desired. The locality hint may be used to identify a lowest level where management of cache avocation is desired and cache memory is allocated at that level and any higher level(s). The locality hint value is based on spatial and/or temporal locality for the data associated with the access. Data is recognized at each cache hierarchy level depending on the attributes associated with the data at a particular level. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.

    A novel processor having shift operations
    35.
    发明专利
    A novel processor having shift operations 未知

    公开(公告)号：AU4595596A

    公开(公告)日：1996-06-19

    申请号：AU4595596

    申请日：1995-12-01

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    A NOVEL PROCESSOR HAVING SHIFT OPERATIONS
    36.
    发明专利
    A NOVEL PROCESSOR HAVING SHIFT OPERATIONS 未知

    公开(公告)号：CA2205830A1

    公开(公告)日：1996-06-06

    申请号：CA2205830

    申请日：1995-12-01

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  MITTAL MILLIND ,  EITAN BENNY ,  MENNENEIER LARRY M ,  YAARI YAAKOV

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

    Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    AN APPARATUS AND A SYSTEM FOR PERFORMING OPERATIONS OF MULTIMEDIA APPLICATIONS AND A METHOD FOR PERFORMING THE SAME
    37.
    发明专利
    AN APPARATUS AND A SYSTEM FOR PERFORMING OPERATIONS OF MULTIMEDIA APPLICATIONS AND A METHOD FOR PERFORMING THE SAME 未知

    公开(公告)号：HK1099095A1

    公开(公告)日：2007-08-03

    申请号：HK07105278

    申请日：2007-05-18

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER D ,  YAARI YAACOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY ,  GLEW ANDREW F ,  DULONG CAROLE ,  KOWASHI EIICHI ,  WITT WOLF

    IPC: G06F20060101 ,  G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F7/60 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78

    Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.

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