公开(公告)号：DE69808020D1

公开(公告)日：2002-10-24

申请号：DE69808020

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

IPC: G06F9/35

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

公开(公告)号：DE69807412D1

公开(公告)日：2002-10-02

申请号：DE69807412

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：AT223082T

公开(公告)日：2002-09-15

申请号：AT98119376

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：AT204393T

公开(公告)日：2001-09-15

申请号：AT98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：WO2008076691A3

公开(公告)日：2008-08-14

申请号：PCT/US2007086968

申请日：2007-12-10

Applicant: MICROCHIP TECH INC ,  LAHTI GREGG D ,  TRIECE JOSEPH W ,  PESAVENTO RODNEY J ,  RAJBHARTI NILESH ,  DAWSON STEVEN

Inventor： LAHTI GREGG D ,  TRIECE JOSEPH W ,  PESAVENTO RODNEY J ,  RAJBHARTI NILESH ,  DAWSON STEVEN

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: A direct memory access (DMA) controller may comprise a DMA bus, a memory coupled to the DMA bus, a DMA engine coupled with the DMA bus, a cyclic redundancy check (CRC) module coupled with the DMA engine, and a bus interface coupled to the DMA engine and the CRC module.

Abstract translation: 直接存储器访问（DMA）控制器可以包括DMA总线，耦合到DMA总线的存储器，与DMA总线耦合的DMA引擎，耦合到DMA引擎的循环冗余校验（CRC）模块和耦合到总线的总线接口 到DMA引擎和CRC模块。

公开(公告)号：WO2008076896A3

公开(公告)日：2008-08-07

申请号：PCT/US2007087600

申请日：2007-12-14

Applicant: MICROCHIP TECH INC ,  PESAVENTO RODNEY J ,  LAHTI GREGG D ,  TRIECE JOSEPH W

Inventor： PESAVENTO RODNEY J ,  LAHTI GREGG D ,  TRIECE JOSEPH W

IPC: G06F12/12

CPC classification number: G06F12/126 ,  G06F12/0862 ,  G06F2212/2022 ,  G06F2212/6022

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

Abstract translation: 用于中央处理单元的高速缓存模块具有与存储器耦合的高速缓存控制单元以及与控制单元和存储器耦合的高速缓存存储器，其中高速缓存存储器具有多个高速缓存行，每个高速缓存行具有用于存储 其中所述多个高速缓存行中的至少一个高速缓存行具有至少一个分支跟踪控制位，所述分支跟踪控制位在被设置时提供所述高速缓存行的自动锁定功能以防在预定义的分支指令具有 已发出。

公开(公告)号：WO03017075A3

公开(公告)日：2003-09-25

申请号：PCT/US0225057

申请日：2002-08-07

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W

IPC: G06F1/32 ,  G06F11/26 ,  G06F11/36

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3287 ,  G06F9/30101 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal out of the plurality of clock signals. The central processing unit comprises an execution unit which controls the select units upon execution of a low power mode instruction to select a clock signal for the central processing unit and the peripheral units.

Abstract translation: 微处理器包括接收第一时钟信号的中央处理单元，接收第二时钟信号的多个外围设备，用于从多个时钟信号中选择第一时钟信号的第一选择单元和用于选择第二时钟信号的第二选择单元 从多个时钟信号中选择一个。 中央处理单元包括执行单元，其在执行低功率模式指令时控制选择单元以选择用于中央处理单元和外围单元的时钟信号。