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    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE
    32.
    发明专利
    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE 未知

    公开(公告)号：FR2982424B1

    公开(公告)日：2014-01-10

    申请号：FR1160209

    申请日：2011-11-09

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： MONFRAY STEPHANE ,  SAVELLI GUILLAUME ,  SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  GAILLARD FREDERIC

    IPC: H01L37/00

    Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.

    33.
    发明专利
    未知

    公开(公告)号：FR2838238B1

    公开(公告)日：2005-04-15

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    Semiconductor device with enveloping gate encapsulated in an insulating medium
    35.
    发明专利
    Semiconductor device with enveloping gate encapsulated in an insulating medium 未知

    公开(公告)号：FR2838238A1

    公开(公告)日：2003-10-10

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    36.
    发明专利
    未知

    公开(公告)号：FR2819341B1

    公开(公告)日：2003-06-27

    申请号：FR0100295

    申请日：2001-01-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  MALLARDEAU CATHERINE

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

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