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    34.
    发明专利
    未知

    公开(公告)号：DE60205909T2

    公开(公告)日：2006-06-08

    申请号：DE60205909

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

    35.
    发明专利
    未知

    公开(公告)号：DE69707666T2

    公开(公告)日：2002-08-08

    申请号：DE69707666

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H03M1/08 ,  H03H11/04 ,  H03H11/12 ,  H03H1/00

    Abstract: An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, comprising: a first resistor (R1) and a first capacitor (C1) which are parallel connected; an operational amplifier (3); a terminal of a second resistor (R2) which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor (R1) and the first capacitor (C1); a second capacitor (C2), which is fedback between the output of the operational amplifier and the inverting input; the filter further comprising an additional pair of resistors (R3A, R3B) which are arranged so as to be fedback between the output and the inverting input, a current signal (IDAC) arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.

    36.
    发明专利
    未知

    公开(公告)号：DE69430525D1

    公开(公告)日：2002-06-06

    申请号：DE69430525

    申请日：1994-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  G11C7/00

    Abstract: An initialization circuit for memory registers (2), being of the type which comprises a signal input (I) being applied a supply voltage (Vp) which rises linearly from a null value, and an initializing output (O) connected to an input of a memory register (2) and on which a voltage signal (Vd) being equal or proportional to the supply voltage (Vp), during the initialization step, and a null voltage signal, upon the supply voltage (Vp) dropping below a predetermined tripping value (Vs), are produced, further comprises, between the input (I) and the output (O): a first circuit portion (3) connected to the input (I), a second circuit portion (4) connected after the first and having a first output (D) connected to the initializing output (O), and a third, inverting circuit portion (7) having an input connected to a second output (C) of the second portion (4) and an output (E) connected to the first portion to even hold off that first portion (3) while the supply voltage drops below the threshold voltage (Vs).

    37.
    发明专利
    未知

    公开(公告)号：DE69517693D1

    公开(公告)日：2000-08-03

    申请号：DE69517693

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLAVALLE CARLO ,  CONFALONIERI PIERANGELO

    IPC: H01L27/02 ,  H01L23/00

    Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, is described. The cells define circuit modules (11) in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips (12, 13; 12, 14) for connection to the supply (Vcc, Vss), at least one of which is in contact (12p, 13n; 14n) with the source regions (4, 5) of MOS transistors of the CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library described also provides a group (1) of cells in which there is provided at least one additional trace which defines an additional strip (15) for connection to the outside (Vb) which is in contact (15s) with the body regions of the MOS transistors of the CMOS pair.

    38.
    发明专利
    未知

    公开(公告)号：DE69413814D1

    公开(公告)日：1998-11-12

    申请号：DE69413814

    申请日：1994-07-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

    Abstract: MOS-transistor switch without body effect comprising a pair of p-channel transistors (M1, M2) inserted in series between two connection terminals (A, B) and a third transistor (M3) with n-channel which is inserted between a connection node of the pair and a minimum potential reference (VSS) and a fourth transistor (M4) with n-channel in parallel with the pair of transistors (M1, M2). The substrates of the transistors of the pair are connected to the connection terminals (A, B). The substrate both of the third transistor (M3) and the fourth transistor (M4) is connected to the potential reference (VSS).

    39.
    发明专利
    未知

    公开(公告)号：DE69316880T2

    公开(公告)日：1998-05-28

    申请号：DE69316880

    申请日：1993-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLAVALLE CARLO ,  CRIPPA CARLO ,  CONFALONIERI PIERANGELO

    IPC: H03G3/20 ,  H03G3/30 ,  H03G5/16

    Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.

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