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    32.
    发明专利
    未知

    公开(公告)号：DE69621020T2

    公开(公告)日：2002-10-24

    申请号：DE69621020

    申请日：1996-11-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  ZAMMATTIO MATTEO ,  COMMODARO STEFANO

    IPC: G05F3/26 ,  G05F3/30

    Abstract: A band-gap reference voltage generator comprises an operational amplifier (2) comprising a first input and a second input, the first input being coupled to a first feedback network (4) and the second input being coupled to a second feedback network (6) both coupled to an output (7) of the operational amplifier providing a reference voltage, the first feedback network containing an emitter-base junction of first bipolar junction transistor means (Q1) and the second feedback network containing an emitter-base junction of second bipolar junction transistor means (Q2), and current supplying means (11) for supplying a bias current to the operational amplifier, the current supplying means being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off, characterized by comprising start-up circuit means (13) activated upon start-up of the reference voltage generator for a fixed, prescribed time interval for forcing a start-up current to flow through the first bipolar junction transistor means (Q1).

    34.
    发明专利
    未知

    公开(公告)号：DE69425367T2

    公开(公告)日：2001-02-15

    申请号：DE69425367

    申请日：1994-04-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

    Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

    37.
    发明专利
    未知

    公开(公告)号：DE69325587D1

    公开(公告)日：1999-08-12

    申请号：DE69325587

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C11/00

    Abstract: A count unit (1) for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter (8) and a number of registers (9, 10) equal in number to the count functions involved. The registers (9, 10) store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter (8) which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One (10) of the registers presents a second parallel input (ADDR) for externally loading an initial data which may be transferred to the other registers (9) via the counter (8).

    38.
    发明专利
    未知

    公开(公告)号：DE69318842T2

    公开(公告)日：1998-12-24

    申请号：DE69318842

    申请日：1993-12-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C8/10 ,  G11C16/06 ,  G11C17/00 ,  G11C8/00

    Abstract: A memory line decoding driver (1) is so biased that the P channel pull-up transistor (6) biasing the final inverter (5) conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage (18) alternatively connects the gate terminal of the pull-up transistor (6) to a capacitor (37), with which the charge is distributed, and to the supply (VPC).

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