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公开(公告)号:DE69613983D1
公开(公告)日:2001-08-23
申请号:DE69613983
申请日:1996-10-30
Applicant: ST MICROELECTRONICS SRL
Inventor: KRAMER ALAN , CANEGALLO ROBERTO , CHINOSI MAURO , GOZZINI GIOVANNI , LEONG PHILIP , ONORATO MARCO , ROLANDI PIER LUIGI , SABATINI MARCO
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公开(公告)号:ITTO991098A1
公开(公告)日:2001-06-14
申请号:ITTO991098
申请日:1999-12-14
Applicant: ST MICROELECTRONICS SRL
Inventor: DE SANDRE GUIDO , PASOTTI MARCO , ROLANDI PIER LUIGI
IPC: G11C16/34
Abstract: The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.
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公开(公告)号:ITTO990943A1
公开(公告)日:2001-04-30
申请号:ITTO990943
申请日:1999-10-29
Applicant: ST MICROELECTRONICS SRL
Inventor: DE SANDRE GUIDO , PASOTTI MARCO , ROLANDI PIER LUIGI , GUAITINI GIOVANNI
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公开(公告)号:IT1305182B1
公开(公告)日:2001-04-10
申请号:ITTO980962
申请日:1998-11-13
Applicant: ST MICROELECTRONICS SRL
Inventor: CANEGALLO ROBERTO , PASOTTI MARCO , ROLANDI PIER LUIGI , GUAITINI GIOVANNI
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公开(公告)号:ITMI991616A1
公开(公告)日:2001-01-22
申请号:ITMI991616
申请日:1999-07-22
Applicant: ST MICROELECTRONICS SRL
Inventor: PASOTTI MARCO , GUAITINI GIOVANNI , ROLANDI PIER LUIGI
IPC: G11C11/56
Abstract: A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits into a respective one of such multi-level non-volatile memory cells by utilizing a multi-level technology. Reading includes the following steps: (c) reading contemporaneously each one of such eight bits which belong to each one of said n bytes by sense amplifiers each connected to each one of such multi-level non-volatile memory cells, (d) assembling such eight bits previously read to form each one of such initial n bytes.
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公开(公告)号:ITTO981003A1
公开(公告)日:2000-05-28
申请号:ITTO981003
申请日:1998-11-27
Applicant: ST MICROELECTRONICS SRL
Inventor: CANEGALLO ROBERTO , GUAITINI GIOVANNI , LHERMET FRANK , PASOTTI MARCO , ROLANDI PIER LUIGI
IPC: G06K20060101 , G11C11/56 , G11C16/12 , G11C27/00
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公开(公告)号:ITTO980962A1
公开(公告)日:2000-05-15
申请号:ITTO980962
申请日:1998-11-13
Applicant: ST MICROELECTRONICS SRL
Inventor: CANEGALLO ROBERTO , PASOTTI MARCO , ROLANDI PIER LUIGI , GUAITINI GIOVANNI
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公开(公告)号:ITTO990943D0
公开(公告)日:1999-10-29
申请号:ITTO990943
申请日:1999-10-29
Applicant: ST MICROELECTRONICS SRL
Inventor: DE SANDRE GUIDO , PASOTTI MARCO , ROLANDI PIER LUIGI , GUAITINI GIOVANNI
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公开(公告)号:ITTO990942D0
公开(公告)日:1999-10-29
申请号:ITTO990942
申请日:1999-10-29
Applicant: ST MICROELECTRONICS SRL
Inventor: DE SANDRE GUIDO , PASOTTI MARCO , ROLANDI PIER LUIGI
IPC: G11C16/12
Abstract: A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.
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公开(公告)号:DE60317457D1
公开(公告)日:2007-12-27
申请号:DE60317457
申请日:2003-01-31
Applicant: ST MICROELECTRONICS SRL
Inventor: PASOTTI MARCO , BORGATTI MICHELE , ROLANDI PIER LUIGI
Abstract: The present invention relates to a 8Mb application-specific embeddable flash memory. It comprises three content-specific I/O ports and delivers a peak read throughput of 1.2GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1 Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18 mu m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 mu m .
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