公开(公告)号：DE69229734D1

公开(公告)日：1999-09-09

申请号：DE69229734

申请日：1992-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03H7/06 ,  H03H7/00 ,  H03H11/34 ,  H03H11/36 ,  H04M1/60 ,  H04M1/76

Abstract: A monolithically integrated AC coupler comprising two capacitors, C1 and C2, respectively connected between an input terminal Vin and an output terminal Vout, and between one said output terminal and a first terminal of connection to a reference potential Vref1. Connected in parallel with the capacitor C1, and serially together, are a capacitor C3 and two field-effect transistors, M1 and M2. Two field-effect transistors, M3 and M4, are connected between the output terminal and a second terminal of connection to a reference potential, Vref2. The connection nodes between the transistors M1 and M2 and between the transistors M3 and M4 are coupled, through two capacitors CS1 and CS2, to the first connection terminal Vref1. The gate terminals of the transistors are applied control signals with two non-overlapping phases, F1 and F2.

公开(公告)号：DE69226021T2

公开(公告)日：1998-10-22

申请号：DE69226021

申请日：1992-09-23

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CONFALONIERI PIERANGELO

IPC: H03K17/06 ,  H03K17/687

Abstract: A driver circuit for an electronic switch (2) which is to be operated from a clock signal (F) having a predetermined frequency, comprises an input pin (A) being applied the clock signal, and a voltage doubler (1) connected between said pin (A) and the switch (2).

公开(公告)号：DE69929201D1

公开(公告)日：2006-02-02

申请号：DE69929201

申请日：1999-10-18

Applicant: ST MICROELECTRONICS SRL

Inventor： GUINEA JESUS ,  TOMASINI LUCIANO ,  MAGGIO SANTO

IPC: H03K5/13 ,  H03L7/00 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033

Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay ( DELTA t) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay ( DELTA t) to the period T. The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay ( DELTA t), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay ( DELTA t) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay ( DELTA t) for locking to the period T.

公开(公告)号：ITVA20010048A1

公开(公告)日：2003-06-23

申请号：ITVA20010048

申请日：2001-12-21

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CLERICI GIANCARLO

IPC: H03F3/45

Abstract: An analog input circuit may include a pair of differential transconductance input stages having input nodes connected in parallel and which are fed the analog input signal. One of the differential transconductance stages may have common mode compatibility toward the supply node at the highest potential, and the other stage may have common mode compatibility toward the supply node at the lowest potential. Furthermore, differential output currents of the transconductance input stages may be summed differentially on first and second input nodes of a differential converter stage, which converts the differential current signals to an amplified differential voltage output signal.

公开(公告)号：IT1311075B1

公开(公告)日：2002-02-28

申请号：ITMI990458

申请日：1999-03-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CLERICI GIANCARLO ,  TOMASINI LUCIANO

IPC: G05F3/16 ,  H03F20060101

Abstract: A fully differential amplifier, in other words one having differential inputs and outputs, is associated with a circuit to regulate the output voltage reference. This circuit contains a resistive divider connected between the output terminals of the differential amplifier, a diode between the intermediate connection of the divider and common bases of load transistors of the differential amplifier, and a current mirror having a first branch connected to a reference voltage generator and a second branch which forms a current generator connected between the common bases of the load transistors and ground. This provides an efficient feedback control system with low power consumption and takes up less space on an integrated circuit.

公开(公告)号：ITMI990458A1

公开(公告)日：2000-09-05

申请号：ITMI990458

申请日：1999-03-05

Applicant: ST MICROELECTRONICS SRL

Inventor： CLERICI GIANCARLO ,  TOMASINI LUCIANO

IPC: G05F3/16 ,  H03F20060101

Abstract: A fully differential amplifier, in other words one having differential inputs and outputs, is associated with a circuit to regulate the output voltage reference. This circuit contains a resistive divider connected between the output terminals of the differential amplifier, a diode between the intermediate connection of the divider and common bases of load transistors of the differential amplifier, and a current mirror having a first branch connected to a reference voltage generator and a second branch which forms a current generator connected between the common bases of the load transistors and ground. This provides an efficient feedback control system with low power consumption and takes up less space on an integrated circuit.

公开(公告)号：DE69228420T2

公开(公告)日：1999-06-24

申请号：DE69228420

申请日：1992-09-16

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H04M19/08

Abstract: A certain amount of DC supply current derivable from a subscriber's line (VL, GROUND) is used for powering at respective regulated voltages a plurality of functional circuits (A,B...) of an equipment connectable to the line. A sensible energy saving can be achieved by splitting the valuable current among the functional circuits, on account of their priority rank, by using at least a differential pair of current delivering transistors (P2,P3). A special circuit monitors the actual current of absorption of the functional circuit of highest rank (A) and produces a control signal that is used for modifying the drive conditions of the current delivering transistors. The current waste caused by sinking a design maximum current through a dissipative shunt voltage regulator of each functional circuit as done in the prior art circuits, is prevented and all the current exceeding the actual absorption needs of the highest rank functional circuit may be distributed to the other functional circuits without waste. This same principle may be advantageously applied also to functional circuits of lesser and lesser rank of priority for maximizing the saving.

公开(公告)号：DE69228807D1

公开(公告)日：1999-05-06

申请号：DE69228807

申请日：1992-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  ERRATICO PIETRO

IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

Abstract: A circuit (1) for synthesizing an impedance associated with a telephone subscriber's circuit (2) connected to a two-wire telephone line (3) is a positive feedback configuration comprising: a single precision resistance (R) connected serially to the line (3); at least one low-pass filter; and an amplifier (7) between the filter (8) and the resistance (R). This circuit (1) allows both the termination impedance and the balance impedance to be synthesized through a single external precision component.

公开(公告)号：IT1315805B1

公开(公告)日：2003-03-26

申请号：ITRM20000032

申请日：2000-01-20

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  GUINEA JESUS ,  CASTELLO RINALDO

IPC: G05F3/24 ,  G05F3/26

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

公开(公告)号：DE69521197T2

公开(公告)日：2001-11-08

申请号：DE69521197

申请日：1995-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  BIETTI IVAN ,  CLERICI GIANCARLO

IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

Abstract: The speech circuit described matches the impedance of the telephone line by synthesizing a complex impedance by means of a positive feedback loop comprising a single resistor (11) and cancels out the side tone by means of a subtracter (20') which extracts from the signal (Va) coming from the line a signal (Vb) correlated to the signal to be transmitted. In order to achieve cancellation of the side tone unaffected by the noise produced in the circuits for synthesizing the impedance, the signal (Vb) correlated to the signal to be transmitted is derived by processing the signal present in the resistor (11) at the output of the feedback loop.