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    EDGE TERMINATION OF HIGH-VOLTAGE SEMICONDUCTOR DEVICE BY RESISTOR-TYPE VOLTAGE DIVIDER
    33.
    发明专利
    EDGE TERMINATION OF HIGH-VOLTAGE SEMICONDUCTOR DEVICE BY RESISTOR-TYPE VOLTAGE DIVIDER 失效

    公开(公告)号：JP2000357796A

    公开(公告)日：2000-12-26

    申请号：JP2000150927

    申请日：2000-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SCHILLACI ANTONIO ,  GRIMALDI ANTONIO ,  FERLA GIUSEPPE

    IPC: H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To resist the high operating voltage whereto a device is subjected, by providing a voltage divider wherein an edge termination includes a plurality of MOS transistors connected in series with each other, and by providing connectively the edge termination between the terminals of a power constituting element whose drivings are impossible. SOLUTION: A device 1 comprises a MOSFET power transistor 21 connected with an edge termination 100. The power transistor 21 is connected in parallel with the series circuit comprising a diode 41 plus the series circuit comprising PMOS parasitic transistors 31, 32, 33, 34. To allow the current flowing from a source terminal S4 of the fourth PMOS parasitic transistor 34 to a source S of the MOSFET power transistor 21, these PMOS parasitic transistors 31-34 are switched on respectively when their respective sources overcome the respective threshold voltages of the PMOS parasitic transistors 31-34. Therefore, there is obtained a limit to the high operating voltage whereto the device 1 is subjected.

    POWER SEMICONDUCTOR DEVICE
    34.
    发明专利
    POWER SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2000138232A

    公开(公告)日：2000-05-16

    申请号：JP28383899

    申请日：1999-10-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: G11C29/14 ,  G11C29/50 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a power device which does not raise problems related to threshold voltage, even if a normal insulating material is used for forming an insulating spacer and will not raise strain causing dislocations or cracks in silicon, even if another material such as silicon nitride is used. SOLUTION: This power semiconductor device has a second insulating material region 10 positioned at a side part of a polysilicon layer 5 and a first insulating material region 6, and at the upper side of a region 14 positioned near the opening at the upper side of an insulation layer body region 2 of a gate oxide layer 4, an oxide region 9 formed between a polysilicon region 5 and the second insulating material region 10, and an oxide spacer 8 formed in the upper side of a second material region.

    SEMICONDUCTOR INTEGRATED ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME
    35.
    发明专利
    SEMICONDUCTOR INTEGRATED ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：JP2003133551A

    公开(公告)日：2003-05-09

    申请号：JP2002203102

    申请日：2002-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CEROFOLINI GIANFRANCO ,  FERLA GIUSEPPE

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L51/00

    Abstract: PROBLEM TO BE SOLVED: To provide a hybrid structure in which organic molecules are bonded with conventional silicon-based microelectronic structure to function as carriers of charged particles. SOLUTION: This MOS transistor structure contains a dielectric oxide layer (3) formed between two silicon plates (1, 2), wherein the silicon plates (1, 2) extend outside the circumference of the oxide layer (3), forming an undercut (5) having a substantially rectangular cross section. The surfaces of the silicon plates (1, 2) are chemically changed to form functional groups (6, 7) that are different from those on the surfaces in the remaining part outside the undercut (5) portion. Organic molecules (8) each having a reversible reduction center and having a molecular length substantially the same as the width of the undercut (5), are selectively reacted with the functional groups (6, 7) on the undercut (5) to form a covalent bond at each end of the organic molecules.

    MONOLYTHIC VERTICAL SEMICONX DUCTOR POWER DEVICE PROVIDED WITH PROTECTION FROM PARASITIC CURRENT
    36.
    发明专利
    MONOLYTHIC VERTICAL SEMICONX DUCTOR POWER DEVICE PROVIDED WITH PROTECTION FROM PARASITIC CURRENT 失效

    公开(公告)号：JPH03173169A

    公开(公告)日：1991-07-26

    申请号：JP30894190

    申请日：1990-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERLA GIUSEPPE ,  PALARA SERGIO

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

    Abstract: PURPOSE: To stabilize the operational characteristics by entirely covering the projecting end of an insulating pocket with a first grounded metallization part. CONSTITUTION: In order to overcome voltage rise at an insulation pocket P caused by the presence of a parasitic transistor, projecting end of the insulating pocket is covered entirely with a metallization part 21, e.g. a metal polysilicide, preferably a platinum layer. It has a resistance of about 1Ω/square which is about 100 times as low as that of the insulation pocket P. Some region of the insulation pocket Preaches a grounded metal track of aluminum and comes into contact therewith. Since the leakage current of parasitic transistors T3, T4 is passed through a low resistance path and grounded, it causes no voltage rise at the insulation pocket P.

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