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公开(公告)号:ITMI913267D0
公开(公告)日:1991-12-05
申请号:ITMI913267
申请日:1991-12-05
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
IPC: H01L21/336 , H01L29/423 , H01L29/78
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公开(公告)号:IT9006610D0
公开(公告)日:1990-05-31
申请号:IT661090
申请日:1990-05-31
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE , GRIMALDI GIUSEPPE
IPC: H01L21/8249 , H01L21/76 , H01L27/06 , H01L27/088 , H01L29/78
Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.
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公开(公告)号:JP2000124410A
公开(公告)日:2000-04-28
申请号:JP28987399
申请日:1999-10-12
Applicant: ST MICROELECTRONICS SRL
Inventor: ZAMBRANO RAFFAELE
IPC: H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/06 , H01L27/10 , H01L27/108 , H01L27/115
Abstract: PROBLEM TO BE SOLVED: To provide a contact structure that has a structural, functional feature to overcome restrictions and/or problems attendant on a usual contact and is easily integrated into an integrated circuit, by a method wherein the contact structure is improved in integration properties to an integrated electronic device equipped with electronic elements formed through a MOS process or the like. SOLUTION: A contact structure is for a semiconductor device equipped with a MOS element 3 and a capacitor element 4 integrated on a semiconductor layer, where a contact 20 is provided inside openings 10 and 11 bored in an insulating layer 12 above a semiconductor layer respectively, and the surface edges, inner walls, and bases of the openings 10 and 11 are covered with a metal layer 18, and the openings 10 and 11 are filled up with insulating resin layer 19.
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公开(公告)号:DE69432407D1
公开(公告)日:2003-05-08
申请号:DE69432407
申请日:1994-05-19
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
IPC: H01L27/08 , H01L21/336 , H01L21/76 , H01L27/088 , H01L29/78 , H01L29/72
Abstract: A Power Integrated Circuit ("PIC") structure comprises a lightly doped semiconductor layer (2;2',2'') of the first conductivity type superimposed over a heavily doped semiconductor substrate (3) of a second conductivity type, wherein a Vertical IGBT and a driving and control circuitry comprising at least first conductivity type-channel MOSFETs are integrated; the MOSFETs are obtained inside well regions (15) of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer (2;2',2'') of the first conductivity type by means of a respective isolated region (12,13) of a second conductivity type.
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公开(公告)号:DE69325994T2
公开(公告)日:1999-12-23
申请号:DE69325994
申请日:1993-05-19
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
Abstract: An integrated structure current sensing resistor for a power MOS device consists of a doped region (20,21,50) extending from a deep body region (2) of at least one cell (1a) of a first plurality of cells, constituting a main power device, to a deep body region (2) of a corresponding cell (1b) of a second smaller plurality of cells constituting a current sensing device.
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公开(公告)号:DE69325645T2
公开(公告)日:1999-12-09
申请号:DE69325645
申请日:1993-04-21
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
Abstract: An integrated structure protection device suitable for protecting a power MOS device from electro static discharges comprises a junction diode (9) comprising a first electrode made of a highly doped region (12) of a first conductivity type surrounded by a body region (11) of a second conductivity type and representing a second electrode of the junction diode (9), which in turn is surrounded by a highly doped deep body region (10) of said second conductivity type. The highly doped region (12) is connected to a polysilicon gate layer (7) representing the gate of the power MOS device, while the deep body region (10) is connected to a source region (6) of the power MOS.
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公开(公告)号:DE69131390T2
公开(公告)日:1999-11-18
申请号:DE69131390
申请日:1991-04-11
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
IPC: H01L21/336 , H01L21/74 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/78 , H01L29/06
Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.
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公开(公告)号:DE69223499T2
公开(公告)日:1998-05-20
申请号:DE69223499
申请日:1992-04-02
Applicant: CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE
IPC: H01L29/78 , H01L21/331 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/735
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公开(公告)号:DE69124289D1
公开(公告)日:1997-03-06
申请号:DE69124289
申请日:1991-05-25
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor: ZAMBRANO RAFFAELE , GRIMALDI ANTONIO
IPC: H01L21/8249 , H01L21/76 , H01L27/06 , H01L27/088 , H01L29/78 , H01L29/772 , H01L29/06
Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.
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公开(公告)号:DE69213675T2
公开(公告)日:1997-02-27
申请号:DE69213675
申请日:1992-11-27
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor: PAPARO MARIO , ZAMBRANO RAFFAELE
Abstract: In the device there are present a first, second and third switch designed to connect a node of the insulation region with a ground node, the collector or drain of the power transistor and a region of a control circuit transistor respectively. The dynamic insulation circuit of the control circuit comprises a pilot circuit which controls: closing of the first switch when the potential of the ground node (or insulation region) is less than the potential of the collector or drain region of the power transistor and the potential of the control circuit region, closing of the second switch and opening of the first when the potential of the collector or drain region of the power transistor is less than the potential of the ground node (or the insulation region), closing of the third switch and opening of the first when the potential of said control circuit region is less than the potential of the ground node (or the insulation region).
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