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    Methode of making a non-volatile MOS semiconductor memory device
    34.
    发明公开
    Methode of making a non-volatile MOS semiconductor memory device 审中-公开
    HerstellungsverfahrenfürFestwert-MOS-Halbleiterspeicherbauelement

    公开(公告)号：EP1675181A1

    公开(公告)日：2006-06-28

    申请号：EP04425937.2

    申请日：2004-12-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tessariol, Paolo ,  Bez, Roberto

    IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate (50), of STI isolation regions (shallow trench isolation) (57) filled by field oxide (65) and of memory cells (500) separated each other by said STI isolation regions (57). The memory cells (500) include a gate electrode (52) electrically isolated from said semiconductor material substrate (50) by a first dielectric layer (53), and the gate electrode includes a floating gate (54) self-aligned to the STI isolation regions (57). The method includes a formation phase of said floating gate (54) exhibiting a substantially saddle shape including a concavity; the formation phase of said floating gate (54) includes a deposition phase of a first conformal conductor material layer (54A).

    Abstract translation: 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底（50）中由场氧化物（65）填充的STI隔离区域（浅沟槽隔离）（57））和存储器单元（ 500）通过所述STI隔离区域（57）彼此分离。 存储单元（500）包括通过第一介电层（53）与所述半导体材料基板（50）电隔离的栅电极（52），并且所述栅电极包括与所述STI隔离自对准的浮栅（54） 地区（57）。 该方法包括所述浮动栅极（54）的形成阶段，其显示包括凹部的基本鞍形; 所述浮置栅极（54）的形成阶段包括第一共形导体材料层（54A）的沉积阶段。

    A content addressable memory cell
    35.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP1526547A1

    公开(公告)日：2005-04-27

    申请号：EP03103898.7

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Process for manufacturing a non-volatile memory cell
    36.
    发明公开
    Process for manufacturing a non-volatile memory cell 审中-公开
    Herstellungsverfahren einer Festwertspeicherzelle

    公开(公告)号：EP1179839A3

    公开(公告)日：2004-12-15

    申请号：EP01114948.1

    申请日：2001-06-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bez, Roberto ,  Camerlenghi, Emilio ,  Ratti Stefano

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L21/28

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

    Abstract translation: 一种用于在半导体衬底上制造非易失性存储单元的工艺包括以下步骤：由氧化物层（2）形成由与衬底隔离的第一多晶硅层（3）组成的堆叠结构; 级联蚀刻第一多晶硅层（3），氧化物层（2）和半导体衬底（1）以限定电池的浮动栅极区域的第一部分和与有源区域（AA）接合的至少一个沟槽（6） 的记忆单元; 用隔离层（7）填充所述至少一个沟槽（6）; 在所述半导体的整个暴露表面上沉积第二多晶硅层（8）; 并蚀刻掉第二多晶硅层（8）以暴露形成在第一多晶硅层（3）中的浮栅区域，从而形成与第一多晶硅层（3）的上述部分相邻的延伸部（9）。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    37.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件，特别是相变存储器，具有硅化方法

    公开(公告)号：EP1439579A1

    公开(公告)日：2004-07-21

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Abstract translation: 的方法worin到绝缘区域（13）在一个主体中形成至少围绕到一半导体主体的阵列部分（51）（10）; 半导体材料的栅极区（16）形成在所述半导体主体的一个电路部分（51）的顶部（10）; 的第一硅化物保护掩模（52）是形成在阵列部分的顶部上; 栅极区（16）和所述电路部（51）的有源区（43）被硅化并且所述第一硅化物保护掩模（52）被去除。 第一硅化物保护掩模（52）是多晶硅，并且与所述栅极区域（16）同时形成。 覆盖所述第一硅化物保护掩模（52）的介电材料的第二硅化物保护掩模（53）的栅极区（16）的硅化之前形成。 第二硅化物保护掩模（53）与形成尾盘反弹到栅极区域（16）间隔件（41）同时形成。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    38.
    发明公开
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    Zellenanordnung mit Bipolar-Auswahl-Transistor和Herstellungsverfahren

    公开(公告)号：EP1408550A1

    公开(公告)日：2004-04-14

    申请号：EP02425605.9

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    Abstract: A cell array (1) is formed by a plurality of cells (2) including each a selection bipolar transistor (4) and a storage component (3). The cell array is formed in a body (10) including a common collector region (11) of P type; a plurality of base regions (12) of N type, overlying the common collector region (11); a plurality of emitter regions (14) of P type formed in the base regions; and a plurality of base contact regions (15) of N type and a higher doping level than the base regions, formed in the base regions (12; 42), wherein each base region (12) is shared by at least two adjacent bipolar transistors (20).

    Abstract translation: 电池阵列包括设置在主体（10）中的P型公共集电极区域（11）上的N型基极区域（12）的数量。 在基极区域中形成P型发射极区域（14）和N型基极接触区域（15），使得基极接触区域的掺杂水平高于基极区域的掺杂水平，并且每个基极区域由 至少两个双极晶体管（20）。 电池阵列制造过程中还包括独立权利要求。

    Phase change memory cell and manufacturing method thereof using minitrenches
    39.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元，并且借助于minitrenches及其制造方法

    公开(公告)号：EP1339110A9

    公开(公告)日：2004-01-28

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

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