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    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages
    31.
    发明公开
    Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages 失效
    在同一半导体芯片上集成具有不同阈值电压的MOS技术的装置的方法

    公开(公告)号：EP0915509A1

    公开(公告)日：1999-05-12

    申请号：EP97830543.1

    申请日：1997-10-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Bolognesi, Davide ,  Magri', Angelo

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

    CPC classification number: H01L29/7802 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238

    Abstract: Process for integrating in a same MOS technology devices with different threshold voltages, characterized by comprising the steps of: simultaneously forming on a semiconductor material layer (2,2') of at least two gate electrodes (5,5';10,10') for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area; selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions (7;7') for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions, and said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.

    Abstract translation: 在具有不同阈值电压，通过包括以下步骤为特征的一个相同的MOS技术的设备工艺处理INTEGRA婷：“至少两个栅电极（5,5的半导体材料层（2,2）”上同时形成; 10,10' ），用于至少两个MOS器件，所述栅极电极包含基本上为直线的部分和角落，具有用于单位面积的respectivement角密度每个栅电极; 在该半导体材料层有选择地将掺杂剂为respectivement沟道区的同时形成（7; 7“），用于所述至少两个MOS器件中，respectivement栅电极之下延伸到所述沟道区域，所述选择性地引入使用作为掩模respectivement 栅电极，从而所述信道区具有，在respectivement栅电极的角部中，掺杂剂浓度比在基本为直线的部分低的，并且所述两个MOS器件因此具有respectivement的阈值电压也依赖于角密度为单位面积和 在栅电极respectivement的角部的孔径角。

    Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof
    33.
    发明公开
    Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof 有权
    相同的功率半导体器件具有绝缘栅和与肖特基二极管和方法用于制备

    公开(公告)号：EP2259327A2

    公开(公告)日：2010-12-08

    申请号：EP10180038.1

    申请日：2002-11-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magrì, Angelo ,  Frisina, Ferruccio

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L29/872

    CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/872

    Abstract: An insulated gate planar power device with a Schottky diode in parallel thereto, said Schottky diode being realized by contacting with a metal layer a semiconductor substrate of a first type of conductivity and the contact zone being laterally surrounded by one or more diffused regions of opposite type of conductivity formed in said substrate for shielding the electric field under conditions of reverse bias of the diode, characterized in that it comprises, in said semiconducting substrate, a buried region doped with a dopant of opposite type of conductivity to that of said semiconductor substrate, geometrically located under said Schottky contact zone and at a greater depth than the depth of said diffused regions.
    A relative process of fabrication is also disclosed.

    Abstract translation: 于此与并联的肖特基二极管的绝缘栅平面功率器件，上述肖特基二极管由具有金属层的第一导电类型和接触区的半导体基片被尾盘反弹由相反类型的一个或多个扩散区域包围接触实现 在所说基片形成了二极管的反向偏置，在没有它包括为特征的条件下，屏蔽电场的导电性，在所述半导体衬底，掩埋区掺杂有相反类型导电性做了所述半导体基底中的掺杂剂时， 几何上位于下所述肖特基接触区域，并在比所述扩散区域的深度更大的深度。 因此制造的相对过程是游离缺失盘。

    Power field effect transistor and manufacturing method thereof
    35.
    发明公开
    Power field effect transistor and manufacturing method thereof 审中-公开
    Leistungsfeldeffekttransistor和Verfahren zu seiner Herstellung

    公开(公告)号：EP1742271A1

    公开(公告)日：2007-01-10

    申请号：EP05425491.7

    申请日：2005-07-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Saggio, Mario Giuseppe ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

    CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7835

    Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1,1a;10,11) with wide band gap comprising the steps of:
    - forming a screening structure (3a,20) on said semiconductor substrate (1,1a;10,11) comprising at least a dielectric layer (2,20) which leaves a plurality of areas of said semiconductor substrate (1,1a;10,11) exposed,
    - carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a first implanted region (4,40),
    carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a second implanted region (6,6c;60,61) inside said at least a first implanted region (4,40),
    - carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4,40;6,60).

    Abstract translation: 一种在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法，包括以下步骤： - 在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20） 至少包括留下所述半导体衬底（1,1a; 10,11）的多个区域的电介质层（2,20），至少在所述半导体衬底中执行第一类型的掺杂剂的离子注入 （1,1a; 10,11）以形成至少第一注入区域（4,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型掺杂剂的离子注入至 在所述至少第一注入区域（4,40）内形成至少第二注入区域（6,6c; 60,61）， - 以低热预算执行所述第一类型和第二类型掺杂剂的激活热处理 适于完成所述至少第一和第二注入区域（4,40; 6,60）的所述形成。

    Single feature size MOS technology power device
    36.
    发明授权
    Single feature size MOS technology power device 失效
    在MOS技术的电力设备与单一的克里提卡尔·马斯

    公开(公告)号：EP0772242B1

    公开(公告)日：2006-04-05

    申请号：EP95830454.5

    申请日：1995-10-30

    Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

    Inventor： Frisina, Ferruccio ,  Magri', Angelo ,  Ferla, Giuseppe

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L21/331

    CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

    Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

    MOS power device with high integration density and manufacturing process thereof
    37.
    发明公开
    MOS power device with high integration density and manufacturing process thereof 审中-公开
    MOS-Leistungsbauelement mit hoher Integrationsdichte und dessen Herstellungsverfahren

    公开(公告)号：EP1450411A1

    公开(公告)日：2004-08-25

    申请号：EP03425099.3

    申请日：2003-02-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo ,  Salinas, Dario

    IPC: H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66712

    Abstract: A MOS power device having: a body (10); gate regions (34) on top of the body (10) and delimiting therebetween a window (40); a body region (35), extending in the body underneath the window; a source region (36), extending inside the body region (35) throughout the width of the window; body contact regions (43), extending through the source region up to the body region; source contact regions (46), extending inside the source region, at the sides of the body contact regions; a dielectric region (41) on top of the source region; openings (42, 45) traversing the dielectric region on top of the body and source contact regions (43, 46); and a metal region (50) extending above the dielectric region (41) and through the first and second openings (42, 45).

    Abstract translation: 一种MOS功率器件，具有：主体（10）; 门区域（34）在主体（10）的顶部上并在其间界定窗口（40）; 身体区域（35），其在所述窗户下方的身体中延伸; 源区域（36），其在所述窗体的整个宽度内在所述体区域（35）内延伸; 身体接触区域（43），延伸穿过源区域直到身体区域; 源极接触区域（46），其在源极区域内延伸，位于身体接触区域的侧面; 在所述源极区域的顶部上的电介质区域（41） 穿过主体顶部的电介质区域和源极接触区域（43,46）的开口（42,45）; 以及在所述电介质区域（41）上方延伸并且穿过所述第一和第二开口（42,45）的金属区域（50）。

    Silicon Schottky barrier diode
    40.
    发明公开
    Silicon Schottky barrier diode 审中-公开
    Schottkydiode aus Silizium

    公开(公告)号：EP1225639A1

    公开(公告)日：2002-07-24

    申请号：EP01830031.9

    申请日：2001-01-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Saggio, Mario ,  Lanois, Frederic ,  Frisina, Ferruccio

    IPC: H01L29/872

    CPC classification number: H01L29/0634 ,  H01L29/872

    Abstract: The present invention relates to a Schottky barrier diode comprising a substrate region (9) of a first conductivity type formed in a semiconductor material layer (10) of same conductivity type and a metal layer (12), characterized in that at least a doped region (13) of a second conductive type is formed in said semiconductor layer (10), each one of said doped regions (13) being disposed under said material layer (10) and being separated from other doped regions (13) by portions of said semiconductor layer (10).

    Abstract translation: 本发明涉及一种肖特基势垒二极管，其包括形成在具有相同导电类型的半导体材料层（10）中的第一导电类型的衬底区域（9）和金属层（12），其特征在于，至少掺杂区域 在所述半导体层（10）中形成第二导电类型（13），每个所述掺杂区域（13）设置在所述材料层（10）的下方，并且与所述第二导电类型的部分与其它掺杂区域（13）分离， 半导体层（10）。

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