公开(公告)号：EP1298670B1

公开(公告)日：2007-03-07

申请号：EP01830614.2

申请日：2001-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: G11C11/56

CPC classification number: G11C19/282 ,  G11C11/5628 ,  G11C11/5642

公开(公告)号：EP1713083A1

公开(公告)日：2006-10-18

申请号：EP05425207.7

申请日：2005-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo

IPC: G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/24

Abstract: The invention relates to a non volatile memory electronic device (20) integrated on semiconductor and of the Flash EEPROM type with NAND architecture comprising at least one memory matrix (21) divided into physical sectors, intended as smallest erasable units, and organised in rows or word lines (WL) and columns or bit lines (BL) of memory cells.
At least one row (ROW_i) or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being completely erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line (SSL) of source line.

Abstract translation: 本发明涉及集成在半导体上的非易失性存储器电子器件（20）和具有NAND架构的闪存EEPROM类型的非易失性存储器电子器件（20），其包括至少一个被划分为物理扇区的存储器矩阵（21），其被设计为最小的可擦除单元， 字线（WL）和存储器单元的列或位线（BL）。 给定物理扇区的至少一行（ROW_i）或字线电连接到相邻物理扇区的至少一行或字线，以形成完全可擦除的单个逻辑扇区，其中相应单元的源终端 该对连接的行指的是源线的相同选择行（SSL）。

公开(公告)号：EP1363292A3

公开(公告)日：2004-07-21

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

公开(公告)号：EP1363292A2

公开(公告)日：2003-11-19

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：EP0825611B1

公开(公告)日：2003-04-09

申请号：EP96830455.0

申请日：1996-08-22

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Calligario, Cristiano ,  Manstretta, Alessandro ,  Torelli, Guido

IPC: G11C11/00

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C16/102 ,  G11C2211/5621

公开(公告)号：EP0785570B1

公开(公告)日：2002-12-04

申请号：EP96830021.0

申请日：1996-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: H01L21/00 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11543

公开(公告)号：EP1170798A1

公开(公告)日：2002-01-09

申请号：EP00204838.7

申请日：2000-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/08 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C16/0491 ,  H01L27/115

Abstract: The invention is referred to a non-volatile memory matrix architecture with virtual ground monolithically integrated on semiconductor and of the type comprising a plurality of memory cells (2), organized into matrix blocks or sectors, which are placed on rows (WL) and columns (BL) and associated to respective row and column decoding circuits, characterized in that said cell blocks or sectors are separated from each other by at least one insulation stripe, which is palallel to the columns (BL).
Advantageously, it is provided a pass-transistor decoding circuitry (10), with a number of levels corresponding to the number of rows to select.

Abstract translation: 本发明涉及一种非易失性存储矩阵体系结构，其中虚拟接地单片集成在半导体上，并且包括多个存储单元（2）的类型，其被组织成矩阵块或扇区，其被放置在行（WL）和列 （BL）并且与相应的行和列解码电路相关联，其特征在于，所述单元块或扇区通过与列（BL）平行的至少一个绝缘条彼此分离。 有利地，提供了一个通过晶体管解码电路（10），其中多个电平对应于要选择的行数。

公开(公告)号：EP1137011A1

公开(公告)日：2001-09-26

申请号：EP00830209.3

申请日：2000-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A nonvolatile memory (1) having a NOR architecture has a memory array (2) including a plurality of memory cells (3) arranged in rows and columns in NOR configuration, the memory cells (3) arranged on a same column being connected to one of a plurality of bit lines (11); and a column decoder (6). The column decoder comprises a plurality of selection stages (17), each of which is connected to respective bit lines (11) and receives first bit line addressing signals (YM 0 , ..., YM 7 ). The selection stages (17) comprise word programming selectors (28) controlled by the first bit line addressing signals (YM 0 , ..., YM 7 ) and supplying a programming voltage (70) to only one of the bit lines (11) of each selection stage (17). Each selection stage (17) moreover comprises a string programming selection circuit (29, 30) controlled by second bit line addressing signals (S 0 , ..., S 7 ) thereby simultaneously supplying the programming voltage (70) to a plurality of the bit lines (11) of each selection stage (17).

Abstract translation: 具有NOR架构的非易失性存储器（1）具有存储器阵列（2），其包括以NOR配置排列成行和列的多个存储单元（3），布置在同一列上的存储单元（3）连接到一个 的多个位线（11）; 和列解码器（6）。 列解码器包括多个选择级（17），每个选择级连接到相应的位线（11）并接收第一位线寻址信号（YM0，...，YM7）。 选择级（17）包括由第一位线寻址信号（YM0，...，YM7）控制的字编程选择器（28），并将编程电压（70）提供给每个位线 选择阶段（17）。 每个选择级（17）还包括由第二位线寻址信号（S0，...，S7）控制的串编程选择电路（29,30），从而同时将编程电压（70）提供给多个位线 （17）的每个选择阶段（11）。

公开(公告)号：EP1124313A1

公开(公告)日：2001-08-16

申请号：EP00830088.1

申请日：2000-02-08

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: H02M3/07

CPC classification number: H02M3/07

Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator (11) and a charge pump (13) and having an output terminal (10); the voltage regulator (11) having a regulation terminal connected to the output terminal (10), and an output (16) supplying a control voltage (V L ); the read charge pump (13) having an output connected to the output terminal (10) and supplying a read voltage (V R ). The device further includes an enable circuit (12) connected to the output (16) and having a pump enable output (17) connected to a charge pump enable terminal (13) and supplying a pump enable signal (PE). The pump enable signal (PE) is set at a first logic level so as to activate the charge pump (13) when the read voltage (V R ) is lower than a nominal value. In addition, the device generates a power-up sync signal (ATDS) which activates a read operation when the read voltage (V R ) reaches its nominal value and a chip enable signal (CE) is set at an active value.

Abstract translation: 一种用于加速包括电压调节器（11）和电荷泵（13）并具有输出端子（10）的多电平非易失性存储器的上电的升压装置; 具有连接到输出端子（10）的调节端子的调压器（11）和提供控制电压（VL）的输出端（16）; 所述读取电荷泵（13）具有连接到所述输出端子（10）并提供读取电压（VR）的输出。 该装置还包括连接到输出端（16）并且具有连接到电荷泵使能端子（13）并提供泵使能信号（PE）的泵使能输出（17）的使能电路（12）。 泵使能信号（PE）被设置在第一逻辑电平，以便当读取电压（VR）低于额定值时激活电荷泵（13）。 此外，器件产生上电同步信号（ATDS），当上述读取电压（VR）达到其标称值且芯片使能信号（CE）被设置为有效值时，该同步信号激活读取操作。

公开(公告)号：EP1063654A1

公开(公告)日：2000-12-27

申请号：EP99830382.0

申请日：1999-06-21

Applicant: STMicroelectronics S.r.l.

Inventor： Barcella, Antonio ,  Rolandi, Paolo

IPC: G11C16/28

CPC classification number: G11C16/28

Abstract: A reading method for non-volatile memory cells is illustrated which comprises a first step in which a memory cell (P2) of the matrix is selected by the row decoder (5) and by the column multiplexer (4), a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell (P2) reaches a defined value and is characterized by a third step during which the selected cell (P2) is read with a sensing ratio depending on the reading voltage of said cell.
Moreover a device for the reading of said cells is described, which comprises a modulation branch (MOD) with at least one selection transistor (MV10) and a load generator (23) associated to said modulation transistor (MV10) in such a way to modulate analogicly the transconductance of one of the two load transistors (M1, M2) in function of the reading voltage of the memory cell (P2).

Abstract translation: 用于非易失性存储单元的读出方法被示出，其包括在其中基质的存储单元（P2）由行解码器选择的第一步骤（5）和由所述列多路复用器（4），预紧的第二步骤 和均衡哪个期间对所选存储器单元（P2）的漏极电极的电压达到规定值，并且是由所选择的小区（P2）在第三步骤期间为特征的读出与在所述的读出电压的感测比例根据 细胞。 更在用于所述单元的读取中描述了一种设备，其与在寻求一种方法来调节相关联的所述调制晶体管（MV10）至少一个选择晶体管（MV10）和负载生成器（23）包括一个调制分支（MOD） 在存储单元（P2）的读出电压的函数的两个负载晶体管（M1，M2）中的一个的analogicly跨导。