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公开(公告)号：JPH07336370A
公开(公告)日：1995-12-22
申请号：JP8793795
申请日：1995-04-13
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO , TAJIKA YOSUKE , SATO MASAKO , SUGIKAWA AKIHIKO , UKITA TERUHIKO , IWAMURA KAZUAKI
IPC: H04B7/26 , H04B10/079 , H04B10/11 , H04B10/114 , H04L12/28 , H04W4/06 , H04W74/08 , H04W84/12
Abstract: PURPOSE:To enable the communication between information equipments only if information equipments are brought by transmitting and receiving communication terminal discrimination information and defining the communicable communication terminals discriminated based on received communication terminal discrimination information as the same group. CONSTITUTION:The communication terminal discrimination information generation part 11 of a communication control part 102 generates communication terminal discrimination information and periodically transmits the information from an antenna 31 via a radio transmission/reception part 103. The communicable terminal discrimination part 14 of the radio transmission/reception part 103 discriminates communicable communication terminals by the communication terminal discrimination information which is received by an antenna 31 and is transmitted from other communication terminal. A group setting part 13 sets the discriminated communicable communication terminals as the same group and a destination header part 12 performs communication with the only other communication terminals within the set same group. Therefore, only if communication terminals approach with each other, communication becomes possible, and a logical communication link with a desired opposite party can be extremely easily set anywhere.
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公开(公告)号：JPH05175853A
公开(公告)日：1993-07-13
申请号：JP34277191
申请日：1991-12-25
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO , SAITOU TATSUNORI
Abstract: PURPOSE:To reduce rendundancy caused by error correction encoding and to improve frequency utilizing efficiency by continuously encoding voice signals in respective classes by one convolutional encoder and afterwads, puncturing the signals at various thinning rates corresponding to error sensitivity. CONSTITUTION:A voice encoder 2 compresses and encodes a voice signal 8, the signals are divided into two classes corresponding to the error sensitivity, and a digital voice signal 9 having high error sensitivity and a digital voice signal 10 having low error sensitivity are outputted. A switch 3 prepares a signal 11 by synthesizing the signals 9 and 10 and supplies the signal 11 to an error correction encoder 4. At the error correction encoder 4, a tail bit is added to the end of the signal 11 only once, and the signal is convolutionally encoded at the same encoding rate. An output signal 12 of the encoder 4 is supplied to a puncture circuit 5, and prescribed bits are erased according to puncture patterns various for each class. A punctured signal 13 is outputted from an output terminal 7.
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公开(公告)号：JPH03234125A
公开(公告)日：1991-10-18
申请号：JP2825390
申请日：1990-02-09
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To select a digital signal subject to error correction from its head bit without delay and to output the result by providing an output selection means selecting one of corrected digital signals based on a syndrome or a residue. CONSTITUTION:A syndrome calculation circuit 1 receives a digital signal 101, calculates the syndrome and outputs the calculated syndrome to a random error estimate circuit 3, a syndrome conversion circuit 5 and an output selection control circuit 21. The syndrome conversion circuit 5 converts the calculated syndrome into a residue and outputs it to a burst error estimate circuit 7. A random error is corrected from a syndrome of the inputted digital signal, a burst error is corrected from the residue of the inputted digital signal and one of the corrected digital signals is selectively outputted. Thus, the output is selected without retarding the corrected digital signal and the error correction time is reduced.
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公开(公告)号：JPH03226122A
公开(公告)日：1991-10-07
申请号：JP2080390
申请日：1990-01-31
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To decrease the circuit scale by calculating a remainder from an inputted digital signal and converting the calculated remainder into a syndrome. CONSTITUTION:A remainder conversion means 21 converting a remainder calculated by a remainder calculation means 19 into a syndrome is provided and the remainder is calculated at first from an inputted digital signal and the remainder is converted into a syndrome. Moreover, a burst error is estimated from the remainder calculated by a burst error estimate circuit 7 and a random error is estimated from the syndrome by the random error estimate circuit 3. Then the error is corrected from the estimated random error pattern and the inputted digital signal and the estimated burst error pattern and a signal in which any of errors is corrected is selectively outputted. Thus, the circuit scale of the remainder calculation circuit 19 and the remainder conversion circuit 21 is decreased and the circuit scale of the entire error correction device is decreased.
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公开(公告)号：JPH03121627A
公开(公告)日：1991-05-23
申请号：JP25981289
申请日：1989-10-04
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To decrease a decoding delay time by implementing the processing in a chain search circuit and an output of error correction/decoding result in parallel. CONSTITUTION:An error correction device used for digital data communication and a digital storage device or the like consists of an input terminal 81, an output terminal 38, a buffer 32, a syndrome calculation circuit 33, a position polynomial calculation circuit 34, a chain search circuit 35, an error numeral calculation circuit 36 and an error correction circuit 37. The error correction circuit 37 outputs the result of error correction and decoding in parallel with the chain search circuit 35 by checking whether or not an error takes place in the order of reception signals with larger suffix. Thus, the time required for decoding is reduced to nearly a half.
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Patent Agency Ranking
公开(公告)号：JPH02301328A
公开(公告)日：1990-12-13
申请号：JP12030389
申请日：1989-05-16
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To decrease the circuit scale by constituting a means setting a circuit calculating the coefficient of an error location polynomial in response to each error number respectively and constituting a means estimating the error location and its magnitude with a common circuit with respect to each error number and generating an error pattern with one and the same circuit. CONSTITUTION:An intermediate switching circuit 16 is provided on an error generating circuit 15 and 1st and 2nd substitute circuits 17, 18 connected switchingly with a switch SW 4 among the circuit 16, an error numer deciding circuit 4 and a syndrome generating circuit 3 are provided respectively. Moreover, a series circuit composed of a chain searching circuit 19 and an error count calculation circuit 20 is interposed between the switching circuit 16 and a subtractor 12 and the error number calculation circuit 20 is connected to the output of the syndrome generating circuit 3. When the coefficient of an error location polynomial is calculated from the syndrome, the coefficient of the error location polynomial is decided in response to the number of errors caused in a reception signal and an error pattern is estimated from one and the same circuit. Thus, the circuit scale is decreased.
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公开(公告)号：JPH01228340A
公开(公告)日：1989-09-12
申请号：JP5362088
申请日：1988-03-09
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO , KODAMA TOMOKO
Abstract: PURPOSE:To perform error correction which allows information transmission requiring real-time processing by providing each of the transmission side and the reception side with a means which adds information for retransmission to each time slot and a retransmission time limiting means which handles information retransmitted within a certain time out of erroneous information as an information signal. CONSTITUTION:In a transmitter 20, packets of plural information signals are collected to constitute each block by a control information adding circuit 2. A block identification number and a check bit for error detection are added to this block by the control information adding circuit 2. Signals led from the adding circuit 2 are temporarily stored in a buffer 3, and a signal having the requested block identification number is outputted to a signal synthesizer 4 when a retransmission request signal is received by a confirmation signal discriminating circuit 7. These signals are erased in the buffer 3 when a certain time elapses after input of signals from the adding circuit 2, and only signals retransmitted within the certain time are handled as information signals. In a receiver 20, it is discriminated by an error detecting circuit 10 whether signals received by a terminal 9 include error or not, and a confirmation signal generator 13 transmits the retransmission request signal to the transmitter 20 through a terminal 14 in accordance with the discrimination result.
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公开(公告)号：JPS6342534A
公开(公告)日：1988-02-23
申请号：JP18650486
申请日：1986-08-08
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO
IPC: H04L1/16
Abstract: PURPOSE:To eliminate the influence due to the error of a backward channel by transmitting not only the confirmation signal of a pertinent frame but also that of plural past frames in case of loop checking of the confirmation signal. CONSTITUTION:A confirmation signal generating part 28 adds redundant bits for error detection to the confirmation signal of L-number of past frames and loop checks these signals together with a frame identification number through a backward line 14 in accordance with an accepted error presence/absence detection result. A confirmation signal discriminating part 24 performs error detection based on a loop checked ACK/NACK signal: and if error is detected, the confirmation signal is abandoned because it is probable that the confirmation signal is erroneous, but otherwise, the received ACK/NACK signal is outputted to a transmission buffer 22. Thus, the influence of error of the backward communication line is loop checked reduced even if there is error in the backward communication line through which the confirmation signal is loop checked and a throughput approximating to the throughput for an errorless ideal case is obtained.
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公开(公告)号：JPS62224132A
公开(公告)日：1987-10-02
申请号：JP6586886
申请日：1986-03-26
Applicant: TOSHIBA CORP
Inventor： TAKADA TAIJI , NAKAMURA MAKOTO
Abstract: PURPOSE:To prevent the deterioration in the system reliability even to a comparatively short code word by detecting a burst error from the result of Viterbi decoding. CONSTITUTION:Line assignment information 21 in 51-bit generated by a transmission data generating section 11 of a master earth station is led to a BCH coder 12 and a check point 12-bit is added to the information point 51-bit to form a 63-bit of coded signal. The result is led to a convolution coder 13, the signal coded into 126-bit code length is led to a satellite line transmitter 14 and sent to a satellite line 31. After a satellite line receiver 15 of a slave earth station receives the signal, the result is led to a Viterbi decoder 16 decoding a convolution code, a 63-bit code is obtained to decode a 2-dimension BCH code. In detecting a burst error as the result, a BCH decoder 17 outputting a burst error detection signal pulse 22 receives the result.
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公开(公告)号：JPS62180634A
公开(公告)日：1987-08-07
申请号：JP2248186
申请日：1986-02-04
Applicant: TOSHIBA CORP
Inventor： UNO SHINTARO , NAKAMURA MAKOTO
Abstract: PURPOSE:To attain always stable synchronization without causing a burst error and to cope with a signal of both 1 4-phase PSK and an offset 4-phase PSK nearly by the same circuit constitution by changing the sampling frequency of the signal of both the 4-phase PSK and offset systems. CONSTITUTION:When a reception signal is a 4-phase PSK signal, the signal is sampled in the same frequency as the data transmission speed of the signal and when the reception signal is an offset 4-phase PSK signal, the signal is sampled by a frequency twice the data transmission speed respectively taking the relation between in-phase component data and orthogonal component data into account, corresponding to 4 case of the recovered carrier phase of 0 deg., 90 deg., 180 deg. and 270 deg., for the in-phase component data and the orthogonal component data of the recovered carrier obtained by receiving/ demodulating the 4-phase PSK signal or the offset 4-phase PSK signal to which a unique word pattern commanding the position of a frame is inserted. Then the pattern of the unique word pattern inserting position in the obtained data and the predetermined unique word pattern are compared. The processing above and the predetermined unique word pattern are compared. The processing above is executed to detect the unique word for the relation of all the in-phase and orthogonal components to be considered, the detection signal is sent to a frame synchronizing circuit to establish the frame synchronization.
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