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公开(公告)号：KR1020080083470A
公开(公告)日：2008-09-18
申请号：KR1020070024079
申请日：2007-03-12
Applicant: 삼성전자주식회사
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/002 , H03M1/06 , H03M2201/62 , H03M2201/644 , H03M2201/814
Abstract: A switching decoder and a current steering digital/analog converter including the same are provided to reduce a glitch by adjusting a size of a PMOS(P-Channel Metal-Oxide Semiconductor) transistor. A switching decoder includes a digital logic circuit(100), and a latch-deglitch circuit(200). The digital logic circuit receives digital signals and generates a couple of control signals. The latch-deglitch circuit has a couple of first transistors and a couple of second transistors. The first transistors receive the couple of control signals, synchronize and output the received control signals with a clock signal. The second transistors are cascade-coupled with the first transistors. The second transistors have a couple of PMOS transistors. Drains of the first transistors cross gates of the second transistors.
Abstract translation: 提供了一种开关解码器和包括该开关解码器的电流转向数字/模拟转换器，以通过调整PMOS（P沟道金属氧化物半导体）晶体管的尺寸来减少毛刺。 开关解码器包括数字逻辑电路（100）和锁存 - 反跳路电路（200）。 数字逻辑电路接收数字信号并产生一对控制信号。 锁存 - 跳跃电路具有一对第一晶体管和一对第二晶体管。 第一晶体管接收一对控制信号，使用时钟信号同步并输出接收到的控制信号。 第二晶体管与第一晶体管级联耦合。 第二晶体管具有一对PMOS晶体管。 第一晶体管的漏极交叉第二晶体管。
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公开(公告)号：KR1020070021059A
公开(公告)日：2007-02-22
申请号：KR1020060076652
申请日：2006-08-14
Applicant: 엡슨 이미징 디바이스 가부시키가이샤
Inventor： 호리바따히로유끼
CPC classification number: H03M1/66 , G02F1/133 , G09G5/006 , H03M2201/814 , H03M2201/8152 , H03M2201/932
Abstract: 본 발명은 용량비를 이용한 디지털 아날로그 변환을 정확하게 행하기 위한 것이다. 0비트째의 데이터는, 충전 제어 트랜지스터(420-0)를 통하여, 캐패시터(430-0)에 공급되고, 1비트째의 데이터는, 충전 제어 트랜지스터(420-1)를 통하여, 캐패시터(430-1)에 공급되며, 2비트째의 데이터는, 충전 제어 트랜지스터(420-2)를 통하여, 캐패시터(430-2)에 공급된다. 그리고, 용량비가 1:2:4로 설정된 캐패시터(430-0, 430-1, 430-2)에 대응하여, 충전 제어 트랜지스터(420-0, 420-1, 420-2)의 트랜지스터를 1:2:4로 설정한다. 이것에 의해, 캐패시터(430-0, 430-1, 430-2)에의 충전을 마찬가지의 조건에서 행할 수 있다.
비디오 라인, 스위치, 수평 전송 레지스터, 앰프, 캐패시터, 트랜지스터, 아날로그 비디오 데이터, 수평 주사 라인Abstract translation: 本发明用于使用容量比精确地执行数字 - 模拟转换。 第0位数据通过充电控制晶体管420-0提供给电容器430-0，第1位数据提供给电容器430- 1，并且第二位数据通过充电控制晶体管420-2被提供给电容器430-2。 然后，将充电控制晶体管420-0,420-1和420-2的晶体管设置为1:2，对应于电容比被设置为1的电容器430-0,430-1和430-2。 2：4。 因此，电容器430-0,430-1和430-2可以在相同条件下充电。
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公开(公告)号：KR1020060014488A
公开(公告)日：2006-02-16
申请号：KR1020040063039
申请日：2004-08-11
Applicant: 삼성전자주식회사
Inventor： 이광희
IPC: H03M1/76
CPC classification number: H03M1/76 , H03M2201/30 , H03M2201/6107 , H03M2201/718 , H03M2201/814 , H03M2201/932
Abstract: 폴링 타임(falling time)을 감소시킬 수 있는 디지털/아날로그 변환기의 최종 출력단의 스위치 구동회로가 개시된다. 본 발명에 의한 스위치 구동회로는 클록 신호에 응답하여 비반전 입력 신호를 제어하는 제1 모스 트랜지스터, 클록 신호에 응답하여 반전 입력 신호를 제어하는 제2 모스 트랜지스터, 비반전 입력 신호를 반전 출력하여 제1 차동입력신호를 출력하는 제1 씨모스 인버터, 반전 입력 신호를 반전 출력하여 제2 차동입력신호를 출력하는 제2 씨모스 인버터, 제1 및 제2 차동입력신호들을 래치하여 제1 및 제2 래치출력신호를 생성하는 제1 래치 및 비반전 및 반전 입력 신호를 래치하여 제3 및 제4 래치출력신호를 생성하는 제2 래치를 구비한 것을 특징으로 한다.
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公开(公告)号：KR200407598Y1
公开(公告)日：2006-02-01
申请号：KR2020050025365
申请日：2005-09-02
Applicant: 채용웅
Inventor： 채용웅
CPC classification number: H03M1/18 , H03M1/002 , H03M1/34 , H03M2201/62 , H03M2201/814 , H03M2201/834
Abstract: 본 고안은 아날로그 메모리를 구비하여 기준전압을 제공하는 아날로그-디지털 변환기에 관한 것으로서, 인젝터와 모스 트랜지스터로 구성되어 소정의 기준전압을 제공하는 다수개의 아날로그 메모리들; 외부 신호와 상기 다수개의 아날로그 메모리들 중 하나로부터 공급되는 기준전압을 입력하고 상기 외부 신호를 상기 기준전압과 비교하는 다수개의 비교기들; 및 상기 다수개의 비교기들로부터 출력되는 신호들을 조합하여 디지털 신호를 출력하는 디코더를 구비함으로써 아날로그-디지털 변환기의 면적이 감소되며, 불필요한 전력 소모를 방지한다.
아날로그 디지털 변환기-
Patent Agency Ranking
公开(公告)号：KR1020040099883A
公开(公告)日：2004-12-02
申请号：KR1020030032013
申请日：2003-05-20
Applicant: 학교법인 정석인하학원
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/0863 , H03M2201/644 , H03M2201/814 , H03M2201/931
Abstract: PURPOSE: A deglitch circuit for improving performance of a digital/analog converter to execute a high-speed data transmission/reception operation is provided to improve the frequency capacity by minimizing the glitch energy. CONSTITUTION: A first PMOS transistor(M1) includes a gate for receiving a positive input signal and is turned on or off according to a logical state of the positive input signal. A first NMOS transistor(M3) includes a drain connected to a drain of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A third NMOS transistor(M5) includes a drain connected to a source of the first PMOS transistor, a gate for receiving the positive input signal, and is turned on or off according to the logical state of the positive input signal. A second PMOS transistor(M2) includes a gate for receiving a negative input signal and is turned on or off according to a logical state of the negative input signal. A second NMOS transistor(M4) includes a drain connected to a drain of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal. A fourth NMOS transistor(M6) includes a drain connected to a source of the second PMOS transistor, a gate for receiving the negative input signal, and is turned on or off according to the local state of the negative input signal.
Abstract translation: 目的：提供一种用于提高数字/模拟转换器执行高速数据发送/接收操作性能的去电泳电路，通过最小化故障能量来提高频率容量。 构成：第一PMOS晶体管（M1）包括用于接收正输入信号的栅极，并根据正输入信号的逻辑状态导通或截止。 第一NMOS晶体管（M3）包括连接到第一PMOS晶体管的漏极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第三NMOS晶体管（M5）包括连接到第一PMOS晶体管的源极的漏极，用于接收正输入信号的栅极，并且根据正输入信号的逻辑状态导通或截止。 第二PMOS晶体管（M2）包括用于接收负输入信号的栅极，并根据负输入信号的逻辑状态导通或截止。 第二NMOS晶体管（M4）包括连接到第二PMOS晶体管的漏极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。 第四NMOS晶体管（M6）包括连接到第二PMOS晶体管的源极的漏极，用于接收负输入信号的栅极，并且根据负输入信号的本地状态导通或截止。
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公开(公告)号：KR1020040020989A
公开(公告)日：2004-03-10
申请号：KR1020020052411
申请日：2002-09-02
Applicant: 엘지전자 주식회사
Inventor： 이승현
IPC: H03M1/66
CPC classification number: H03M1/76 , H03M2201/61 , H03M2201/814
Abstract: PURPOSE: A digital/analog converter is provided to reduce a turn-on resistance of an NMOS transistor of a switching unit by applying the electric potential of high level to a gate of the NMOS transistor of the switching unit. CONSTITUTION: A digital/analog converter includes a resistance sequence(20), a plurality of invert/level shifters(21-1 to 21-4), and a plurality of switching unit(22-1 to 22-4). The resistance sequence(20) is formed with a plurality of resistors in order to generate analog signals corresponding digital signals. The invert/level shifters(21-1 to 21-4) are used for inverting the digital codes and elevating the operating levels of the digital codes to higher levels. The switching units(22-1 to 22-4) are selectively operated according to the digital codes and the output signals of the invert/level shifters(21-1 to 21-4) in order to pass the analog signals of the resistance sequence(20).
Abstract translation: 目的：提供数字/模拟转换器，通过将高电平的电位施加到开关单元的NMOS晶体管的栅极来降低开关单元的NMOS晶体管的导通电阻。 构成：数字/模拟转换器包括电阻序列（20），多个反相/电平移位器（21-1至21-4）和多个开关单元（22-1至22-4）。 电阻序列（20）由多个电阻器形成，以便产生对应数字信号的模拟信号。 反相/电平移位器（21-1至21-4）用于反转数字代码并将数字代码的操作电平提升到更高的水平。 开关单元（22-1至22-4）根据数字代码和反相/电平移位器（21-1至21-4）的输出信号选择性地工作，以便通过电阻序列的模拟信号 （20）。
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公开(公告)号：KR1020020072627A
公开(公告)日：2002-09-18
申请号：KR1020010012545
申请日：2001-03-12
Applicant: 학교법인 정석인하학원
IPC: H03M1/12
CPC classification number: H03M1/141 , H03M2201/62 , H03M2201/814
Abstract: PURPOSE: A current-driven folding/interpolating analog/digital converter is provided, which has a small chip area and a low power consumption and has a fast signal processing speed. CONSTITUTION: A reference voltage generation part(10) generates a reference voltage to compare with an analog input of a folding amplification stage. An arithmetic folding part(20) has a plurality of arithmetic folding blocks outputting a pair of positive and negative waveforms by preprocessing a sinusoidal folding signal having multi cross points by receiving an input signal. A current-driven interpolating circuit(30) outputs folding signals having cross points of additional equivalent gap from the folding signal generated from two random adjacent arithmetic folding blocks of the arithmetic folding part. A current comparator part(40) converts a plurality of full differential folding current signals obtained from the interpolating circuit into a plurality of circular codes. And a digital encoder part(50) converts the plurality of circular codes from the current comparator part into encoded digital signals.
Abstract translation: 目的：提供电流驱动的折叠/内插模拟/数字转换器，具有小的芯片面积和低功耗，并具有快速的信号处理速度。 构成：参考电压产生部分（10）产生参考电压以与折叠放大级的模拟输入进行比较。 算术折叠部分（20）具有通过接收输入信号预处理具有多个交叉点的正弦折叠信号而输出一对正和负波形的多个算术折叠块。 电流驱动内插电路（30）从由算术折叠部分的两个随机相邻算术折叠块产生的折叠信号输出具有额外等效间隙的交叉点的折叠信号。 电流比较器部分（40）将从内插电路获得的多个全差分折叠电流信号转换为多个循环码。 并且数字编码器部分（50）将来自当前比较器部分的多个圆形码转换成编码的数字信号。
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公开(公告)号：KR1020000050404A
公开(公告)日：2000-08-05
申请号：KR1019990000265
申请日：1999-01-08
Applicant: 삼성전자주식회사
Inventor： 백승범
CPC classification number: H03M1/70 , H03M2201/62 , H03M2201/814
Abstract: PURPOSE: A digital analog converter is provided to increasing an output range from a ground voltage to a voltage source level by constructing a DAC current source circuit using first and second current source circuits. CONSTITUTION: A bias circuit(100) generates first to fourth bias voltages of the same level. A first current source circuit(260) generates a first output voltage in response to the first and second bias voltage and first and second clock signals. A second current source circuit(270) generates a second output voltage in response to the third and fourth bias voltages and third and fourth clock signals. A decoding logic unit(210) generates the first to fourth clock signals and an output selection signal for selecting an output voltage when digital data to be converted is inputted.
Abstract translation: 目的：提供数字模拟转换器，通过使用第一和第二电流源电路构造DAC电流源电路来增加从地电压到电压源电平的输出范围。 构成：偏置电路（100）产生相同电平的第一至第四偏置电压。 第一电流源电路（260）响应于第一和第二偏置电压以及第一和第二时钟信号产生第一输出电压。 第二电流源电路（270）响应于第三和第四偏置电压以及第三和第四时钟信号产生第二输出电压。 解码逻辑单元（210）产生第一至第四时钟信号和用于在输入要转换的数字数据时选择输出电压的输出选择信号。
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公开(公告)号：KR1020000009810A
公开(公告)日：2000-02-15
申请号：KR1019980030447
申请日：1998-07-28
Applicant: 삼성전자주식회사
Inventor： 손일영
IPC: H03M1/36
CPC classification number: H03M1/0818 , H03M1/124 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: Analog-to-digital converter having a CMOS comparator reduces noises generated by a clock. CONSTITUTION: A first input terminal receives a first input signal(INPUT1). A second input terminal receives a second input signal(INPUT2). A first node generates a first output signal. A second node generates a second output signal. A first input circuit(10) receives a first input signal from the first input terminal. A second input circuit(20) receives a second input signal from the second input terminal. A reset transistor performs a conversion between the tracking mode and the sampling mode. A first latch circuit(50) is connected among a power voltage and the first and second nodes, and amplifies first and second output signals. A second latch circuit(60) is connected among the first and second nodes and the reset transistor. A bias circuit(40) provides a current. An output circuit(INV11,INV12) outputs first and second output signals amplified by the first and second latch circuits. The reset transistor receives a clock signal at its own gate, a source and drain of which are connected between the bias circuits. Thereby, the DAC's performance drop caused by a clock noise can be prevented.
Abstract translation: 目的：具有CMOS比较器的模数转换器可减少时钟产生的噪声。 构成：第一输入端接收第一输入信号（INPUT1）。 第二输入端子接收第二输入信号（INPUT2）。 第一节点产生第一输出信号。 第二节点产生第二输出信号。 第一输入电路（10）从第一输入端子接收第一输入信号。 第二输入电路（20）从第二输入端子接收第二输入信号。 复位晶体管执行跟踪模式和采样模式之间的转换。 第一锁存电路（50）连接在电源电压和第一和第二节点之间，并放大第一和第二输出信号。 在第一和第二节点和复位晶体管之间连接第二锁存电路（60）。 偏置电路（40）提供电流。 输出电路（INV11，INV12）输出由第一和第二锁存电路放大的第一和第二输出信号。 复位晶体管在其自身的栅极接收时钟信号，其源极和漏极连接在偏置电路之间。 因此，可以防止由时钟噪声引起的DAC的性能下降。
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