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公开(公告)号：KR1020010008374A
公开(公告)日：2001-02-05
申请号：KR1020000071360
申请日：2000-11-28
Applicant: 주식회사 나노위즈
IPC: H03M1/12
CPC classification number: H03M1/14 , H03M2201/8152 , H03M2201/932
Abstract: PURPOSE: A merged capacitor switching structure of a pipeline analog to digital converter is provided to reduce a load capacitance by merging two capacitors to reduce the number of the required capacitors, thereby increasing the speed of an amplifier by two times without increasing the power consumption. CONSTITUTION: The device is composed of a plurality of capacitors(C1-C16) for storing an analog input voltage, an amplifier for amplifying and outputting a residual voltage through the capacitors, a 4 bits of flash converter(50) connected to an input terminal and a decoding circuit(60) for controlling a switch depending on a digital code. The merged capacitor switching structure merges two capacitors(C1,C2) in which an identical voltage is applied and the stored charge amount is same among the plurality of capacitors, and forms one capacitor(C1'), wherein a capacitor(C2') is grounded.
Abstract translation: 目的：提供一种流水线模数转换器的并联电容器开关结构，通过合并两个电容来减少负载电容，减少所需电容的数量，从而将放大器的速度提高两倍，而不增加功耗。 构成：该装置由用于存储模拟输入电压的多个电容器（C1-C16），用于放大并通过电容器输出剩余电压的放大器组成，连接到输入端子的4位闪存转换器（50） 以及用于根据数字代码控制开关的解码电路（60）。 合并电容器开关结构合并在多个电容器中施加相同电压的两个电容器（C1，C2）和存储的电荷量相同，形成一个电容器（C1'），其中电容器（C2'）为 接地。
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公开(公告)号：KR1020140047200A
公开(公告)日：2014-04-22
申请号：KR1020120111242
申请日：2012-10-08
Applicant: (주)참케어
Inventor： 이동화
IPC: H03M1/12
CPC classification number: H03M1/34 , H03M1/129 , H03M2201/61 , H03M2201/6157 , H03M2201/622 , H03M2201/932
Abstract: The present invention discloses an analog-to-digital converting system capable of accurate conversion even if the peak-to-peak voltage of an analog signal is low. The analog-to-digital converting system according of the present invention is configured to include an amplification part (210), an analog-to-digital converter (ADC) (220), an integrator (230), an attenuator (240), and a digital-to-analog converter (DAC) (250). The analog-to-digital converting system and converting method according to the present invention has the advantage of generating a digital signal with accuracy and a high resolution even when the peak-to-peak voltage of the analog signal is low.
Abstract translation: 本发明公开了即使模拟信号的峰 - 峰电压低的能够进行精确转换的模数转换系统。 根据本发明的模拟 - 数字转换系统被配置为包括放大部分（210），模数转换器（ADC）（220），积分器（230），衰减器（240） 和数模转换器（DAC）（250）。 根据本发明的模数转换系统和转换方法具有即使在模拟信号的峰 - 峰电压低的情况下也产生具有精度和高分辨率的数字信号的优点。
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33.发明公开Weighted Capacitor Digital-to-Analog Converter adopting charge sharing scheme 无效加权电容数字模拟转换器采用电荷共享方案
公开(公告)号：KR20120012051A
公开(公告)日：2012-02-09
申请号：KR20100073922
申请日：2010-07-30
Applicant: KOREA ELECTRONICS TECHNOLOGY
Inventor： KIM JIN SUP , LIM TAE HO
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/002 , H03M2201/6107 , H03M2201/8152 , H03M2201/932
Abstract: PURPOSE: A WCDAC(Weighted Capacitor Digital-To-Analog Converter) using a charge sharing technique is provided to ensure a reduced chip area by reducing the size of a capacitor at the time of design of the WCDAC. CONSTITUTION: A WCDAC comprises an electric charge-non sharing charge unit(110), an electric charge-sharing charge unit(120), and an output unit(130). The electric charge-non sharing charge unit converts upper bits of digital data into analogue data. The electric charge-sharing charge unit is charged with electric charges corresponding to the data amount of the upper bits for the digital-to-analogue conversion. The electric charge-non sharing charge unit outputs the charged electric charges to the output unit. The electric charge-sharing charge unit converts lower bits of the digital data into analogue data. The output unit outputs the analog signal corresponding to the digital data based on the electric charges outputted the electric charge-non sharing charge unit.
Abstract translation: 目的：提供使用电荷共享技术的WCDAC（加权电容数模转换器），以通过在设计WCDAC时减小电容器的尺寸来确保减小的芯片面积。 构成：WCDAC包括电荷非共享充电单元（110），电荷共享充电单元（120）和输出单元（130）。 电荷非共享充电单元将高位数字数据转换为模拟数据。 电荷共享充电单元对与数字到模拟转换的高位的数据量相对应的电荷充电。 电荷非共享充电单元将充电的电荷输出到输出单元。 电荷共享充电单元将数字数据的低位转换为模拟数据。 输出单元基于输出电荷非共享费用单元的电荷输出与数字数据对应的模拟信号。
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公开(公告)号：KR1020110106559A
公开(公告)日：2011-09-29
申请号：KR1020100025653
申请日：2010-03-23
Applicant: 선문대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M2201/62 , H03M2201/8152 , H03M2201/932
Abstract: 본 발명의 디지털 아날로그 컨버터는, n비트 디지털 입력데이터를 아날로그 출력데이터로 변환하는 디지털 아날로그 컨버터에 있어서, 제1클럭에 의해 스위칭되어 제1전압 입력단자에 전기적으로 연결됨으로써 제1전압을 전달하는 제1 연결스위치; n/2개의 상위비트 디지털 입력데이터의 논리 레벨에 따라 각각 스위칭되어, 제1 연결스위치를 통하여 전달된 제1전압에 해당하는 전압을 전달하는 n/2개의 상위비트 데이터스위치부; n/2개의 하위비트 디지털 입력데이터의 논리 레벨에 따라 각각 스위칭되어, 제2전압 입력단자의 제2전압에 해당하는 전압을 전달하는 n/2개의 하위비트 데이터스위치부; 각각의 일측단자와 타측단자에 전달되는, n/2개의 상위비트 데이터스위치부로부터의 전압과, n/2개의 하위비트 데이터스위치부로부터의 전압을 인가받아 각각의 전하량을 충전하는 n/2개의 가중치 커패시터; 제2클럭에 의해 스위칭되어 n/2개의 상위비트 데이터스위치부에 전기적으로 연결됨으로써 n/2개의 가중치 커패시터의 합산된 전하량을 전달하는 제2 연결스위치; 및 제2 연결스위치를 통하여 전달되는, n/2개의 가중치 커패시터의 합산된 전하량에 해당하는 값을 입력하여 해당하는 아날로그 출력데이터를 출력하는 신호출력부를 포함하는 것을 특징으로 한다.
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公开(公告)号：KR1020110047406A
公开(公告)日：2011-05-09
申请号：KR1020090104020
申请日：2009-10-30
Applicant: 인하대학교 산학협력단
CPC classification number: H03M3/04 , H03M2201/644 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: A differential switch circuit using an NAND gate and a source amplifier is provided to reduce the over-drive voltage by reducing a swing width of a digital signal applied to a differential switch. CONSTITUTION: A current generating unit(100) is connected to a first common node(CN1) to receive uniform static current. A differential switch unit(300) is connected to the current generating unit through a first common node, and supplies uniform static current. A switch driving circuit unit(500) includes a first source amplifier(510) connected to a third NMOS transistor, a second source amplifier(530) connected to a fourth NMOS transistor, and a NAND gate connected to the first and second source amplifiers.
Abstract translation: 目的：提供使用NAND门和源极放大器的差分开关电路，通过减小施加到差分开关的数字信号的摆幅来减小过驱动电压。 构成：电流产生单元（100）连接到第一公共节点（CN1）以接收均匀的静态电流。 差动开关单元（300）通过第一公共节点连接到电流发生单元，并提供均匀的静态电流。 开关驱动电路单元（500）包括连接到第三NMOS晶体管的第一源极放大器（510），连接到第四NMOS晶体管的第二源极放大器（530）和连接到第一和第二源极放大器的与非门。
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Patent Agency Ranking
公开(公告)号：KR1020090106229A
公开(公告)日：2009-10-08
申请号：KR1020080031796
申请日：2008-04-04
Applicant: 포항공과대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/662 , H03M2201/61 , H03M2201/62 , H03M2201/625 , H03M2201/932
Abstract: PURPOSE: A digital to analog converter with high resolution is provided to reduce the area of a circuit by a layout and a manufacturing cost by simplifying a circuit configuration. CONSTITUTION: A first DAC(110) receives a first digital signal and outputs a first analog signal. A second DAC(120) receives a second digital signal and outputs a second digital signal. An attenuator(140) attenuates the second analog signal. A signal synthesizer(150) synthesizes the first analog signal and the attenuated second analog signal.
Abstract translation: 目的：提供高分辨率的数模转换器，通过简化电路配置，通过布局和制造成本降低电路面积。 构成：第一DAC（110）接收第一数字信号并输出第一模拟信号。 第二DAC（120）接收第二数字信号并输出第二数字信号。 衰减器（140）衰减第二模拟信号。 信号合成器（150）合成第一模拟信号和衰减的第二模拟信号。
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公开(公告)号：KR100789700B1
公开(公告)日：2008-01-02
申请号：KR1020060076927
申请日：2006-08-16
Applicant: 주식회사 실리콘웍스
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/002 , H03M2201/62 , H03M2201/932
Abstract: A digital to analog converter having a pseudo segment resistor cell is provided to reduce the area of a layout and power consumption by employing the pseudo segment resistor cell. A digital to analog converter(300) includes a resistor array(310) and a switch block(320). The resistor array outputs a plurality of segment voltages(VR1~VR257) having the voltage level between a reference highest voltage(VR-MAX) and a reference lowest voltage(VR-MIN). The switch block divides digital data into front data and termination data, selects a segment reference highest voltage and a segment reference lowest voltage of the front data among the plurality of segment voltages, generates a segment highest voltage(VRH), a segment lowest voltage(VRL), and at least one pseudo segment voltage by using the segment reference highest voltage and the segment reference lowest voltage, and selects and outputs the voltage corresponding to the rear data among the segment highest voltage, the segment lowest voltage, and the at least one pseudo segment voltage.
Abstract translation: 提供具有伪分段电阻单元的数模转换器，以通过使用伪分段电阻单元来减小布局和功耗的面积。 数模转换器（300）包括电阻阵列（310）和开关块（320）。 电阻器阵列输出具有参考最高电压（VR-MAX）和参考最低电压（VR-MIN）之间的电压电平的多个段电压（VR1〜VR257）。 开关块将数字数据分割成前面的数据和终止数据，在多个段电压中选择前段数据的段参考最高电压和段参考最低电压，产生段最高电压（VRH），段最低电压（ VRL），以及通过使用段参考最高电压和段参考最低电压至少一个伪段电压，并且选择并输出对应于段最高电压，段最低电压和至少 一个伪段电压。
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公开(公告)号：KR1020070060589A
公开(公告)日：2007-06-13
申请号：KR1020050120327
申请日：2005-12-09
Applicant: 엘지디스플레이 주식회사
CPC classification number: H03M1/66 , G02F1/133 , G09G3/36 , H03M2201/62 , H03M2201/932
Abstract: A digital to analog converter is provided to reduce a manufacturing cost and minimize an area by using both a decoder method and a binary method. A digital to analog converter includes a first control unit(101), and a second control unit(103). The first control unit(101) selects at least one analog level signal of a plurality of analog level signals which are modulated by a predetermined lower bit data signal of n-bit data signals and controlled by the modulated signal. The second control unit(103) is connected to the first control unit(101), and selects and outputs any one level of at least more one analog level which are controlled by a predetermined upper bit data signal of the n-bit data signals. The upper bit data signal has the uppermost one bit. The lower bit data signal has n-1 bits. A decoder(115) modulates the lower bit data signal by an exponent of two. A first transistor group has double times as many as the number of signals which are modulated by the exponent of two.
Abstract translation: 提供数模转换器以通过使用解码器方法和二进制方式来减少制造成本并使面积最小化。 数模转换器包括第一控制单元（101）和第二控制单元（103）。 第一控制单元（101）选择多个模拟电平信号的至少一个模拟电平信号，该模拟电平信号由n位数据信号的预定低位数据信号调制并由调制信号控制。 第二控制单元（103）连接到第一控制单元（101），并且选择并输出由n位数据信号的预定高位数据信号控制的至少一个模拟电平的任何一个电平。 高位数据信号具有最高一位。 低位数据信号具有n-1位。 解码器（115）以低于2的指数调制低位数据信号。 第一晶体管组是由两个指数调制的信号的数量的两倍。
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公开(公告)号：KR1020060011520A
公开(公告)日：2006-02-03
申请号：KR1020040060403
申请日：2004-07-30
Applicant: 매그나칩 반도체 유한회사
Inventor： 김정민
CPC classification number: H03M1/668 , G09G3/20 , H03M1/06 , H03M1/76 , H03M2201/6107 , H03M2201/814 , H03M2201/932
Abstract: 본 발명은 오버슈트가 발생하지 않아 고속으로 동작할 수 있는 전류구동 디지털아날로그변환장치를 제공하기 위한 것으로, 이를 위한 본 발명으로 서로 다른 복수의 아날로그전류량을 공급하기 위한 전류공급부; 복수비트의 디지털신호를 입력받아 이에 대응하는 상기 아날로그전류량을 출력하기 위한 제1 디지털아날로그변환부; 반전된 상기 복수의 디지털아날로그신호를 입력받아 상기 제1 디지털아날로그변환부와 상보적으로 구동하여 대응하는 상기 아날로그전류량을 출력하기 위한 제2 디지털아날로그변환부; 상기 제1 디지털아날로그변환부에 접속되어, 상기 제1 디지털아날로그변환부의 출력전류를 미러링하여 아날로그신호를 출력하기 위한 제1 로딩부; 및 상기 제2 디지털아날로그변환부의 출력전류를 공급받아 상기 제1 로딩부에 의해 상기 제1 디지털아날로그변환부에 걸리는 바이어스전압과 실질적으로 동일한 전압이 상기 제2 디지털아날로그변환부에 공급되도록 하기 위한 제2 로딩부를 구비하는 디지털아날로그변환장치를 제공한다.
오버슈트(Over Shoot), 고속동작, 스위칭, 안정화시간(settling time), 로드-
公开(公告)号：KR1020040016587A
公开(公告)日：2004-02-25
申请号：KR1020020048831
申请日：2002-08-19
Applicant: 이디텍 주식회사
IPC: H03M1/54
CPC classification number: G11C27/02 , H03M1/1245 , H03M2201/932
Abstract: PURPOSE: A track and hold circuit of an A/D converter mounted video output system is provided to reduce the leakage current under the low voltage by connecting a double dummy switch to a sampling switch. CONSTITUTION: A track and hold circuit mounted in an A/D converter for video output system includes a sampling switch(2), the first MOS dummy switch(3), the second MOS dummy switch(4), a PLL clock generator(5), a capacitor(6), and a source follower amplifier(7). The sampling switch(2) is used for switching to sample or hold an analog video output signal. The first MOS dummy switch(3) is used for holding the parasitic capacitance and minimizing the leakage current of the sampling switch. The second MOS dummy switch(4) is used for removing the parasitic capacitance and the leakage current by complement of the first MOS dummy switch(3). The PLL clock generator(5) is operated by the sampling switch, the first MOS dummy switch(3), and the second MOS dummy switch(4) and provides a system clock pulse signal. The capacitor(6) is charged or discharged according to the sampling switch. The source follower amplifier(7) is used for amplifying an output voltage of the sampling switch and a discharge voltage of the capacitor.
Abstract translation: 目的：提供A / D转换器安装的视频输出系统的跟踪和保持电路，通过将双虚拟开关连接到采样开关来降低低电压下的漏电流。 构成：安装在视频输出系统的A / D转换器中的轨道和保持电路包括采样开关（2），第一MOS虚拟开关（3），第二MOS虚拟开关（4），PLL时钟发生器（5） ），电容器（6）和源极跟随放大器（7）。 采样开关（2）用于开关采样或保持模拟视频输出信号。 第一MOS虚拟开关（3）用于保持寄生电容并使采样开关的漏电流最小化。 第二MOS虚拟开关（4）用于通过第一MOS虚拟开关（3）的互补来去除寄生电容和漏电流。 PLL时钟发生器（5）由采样开关，第一MOS虚拟开关（3）和第二MOS虚拟开关（4）操作，并提供系统时钟脉冲信号。 电容器（6）根据采样开关进行充放电。 源极跟随放大器（7）用于放大采样开关的输出电压和电容器的放电电压。
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