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    SURFACE PROPERTIES OF POLYMERIC MATERIALS WITH NANOSCALE FUNCTIONAL COATING
    31.
    发明申请
    SURFACE PROPERTIES OF POLYMERIC MATERIALS WITH NANOSCALE FUNCTIONAL COATING 审中-公开
    聚合物与纳米功能涂料的表面性能

    公开(公告)号：US20150103504A1

    公开(公告)日：2015-04-16

    申请号：US14579464

    申请日：2014-12-22

    Applicant: Edward Maxwell Yokley ,  Yaw Samuel Obeng

    Inventor： Edward Maxwell Yokley ,  Yaw Samuel Obeng

    IPC: H05K1/18

    CPC classification number: H05K1/185 ,  B05D1/62 ,  B05D3/142 ,  B05D3/144 ,  B29C59/14 ,  C03C23/006 ,  C03C2218/31 ,  H05K3/284 ,  H05K2201/0104 ,  H05K2201/0195 ,  H05K2201/09872 ,  H05K2203/095

    Abstract: An electronic device comprising a substrate having a component-side surface and a moisture protection film covering the component-side surface. The moisture protection film includes a first water layer bonded to component-side surface that is an activated surface, wherein the activated surface has a lower water contact angle than the substrate surface before the surface activation. The film includes a first graphed layer of a plasma-reacted first set of precursor molecules graphed to the first water layer, wherein the first water layer forms a first bonding link between the substrate surface and the reacted first set precursor molecules. The film includes a second water layer bonded to the first graphed layer. The film includes a second graphed layer of a plasma-reacted second set of precursor molecules graphed to the second water layer, wherein the second water layer forms a second bonding link between the second water layer and the reacted second set of precursor molecules.

    Abstract translation: 一种电子设备，包括具有组件侧表面的基板和覆盖所述元件侧表面的防潮膜。 防潮膜包括结合到作为活化表面的组分侧表面的第一水层，其中活化表面在表面活化之前具有比衬底表面更低的水接触角。 薄膜包括第一层图形化的第一组前体分子，其绘制在第一水层上，其中第一水层形成衬底表面和反应的第一组前体分子之间的第一键合连接。 膜包括结合到第一图形层的第二水层。 薄膜包括被绘制到第二水层的等离子体反应的第二组前体分子的第二图形层，其中第二水层在第二水层和反应的第二组前体分子之间形成第二键合连接。

    Power Semiconductor Module and Method for Producing a Power Semiconductor Module
    32.
    发明申请
    Power Semiconductor Module and Method for Producing a Power Semiconductor Module 有权
    功率半导体模块及其制造功率半导体模块的方法

    公开(公告)号：US20150092376A1

    公开(公告)日：2015-04-02

    申请号：US14499915

    申请日：2014-09-29

    Applicant: Infineon Technologies AG

    Inventor： Andre Arens ,  Juergen Hoegerl ,  Magdalena Hoier

    IPC: H05K1/11 ,  H05K1/18 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00

    CPC classification number: H05K1/111 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/181 ,  H05K3/28 ,  H05K3/284 ,  H05K7/1432 ,  H05K2201/0104 ,  H05K2201/042 ,  H05K2201/10303 ,  H05K2201/10318 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

    Abstract translation: 印刷电路板（PCB）具有布置在其顶侧的第一结构化金属化和在垂直方向上布置在第一金属化下方的至少一个第二金属化，平行于第一金属化并与其绝缘。 在PCB顶侧也是裸露的半导体芯片，其具有通过接合线连接到PCB顶面上的第一金属化的相应接触焊盘的接触电极。 在操作期间，接触电极和对应的接触垫的第一部分承载高电压。 所有高电压接触焊盘通过电镀通孔导电连接到第二金属化。 绝缘层完全覆盖芯片周围的芯片和PCB的界定区域，并且所有高压承载接触焊盘和电镀通孔完全被绝缘层覆盖。 在操作期间，接触电极和对应的接触焊盘的第二部分处于低电压。

    Boron nitride/resin composite circuit board, and circuit board including boron nitride/resin composite integrated with heat radiation plate
    39.
    发明授权
    Boron nitride/resin composite circuit board, and circuit board including boron nitride/resin composite integrated with heat radiation plate 有权
    氮化硼/树脂复合电路板，以及包含氮化硼/树脂复合材料与散热板一体化的电路板

    公开(公告)号：US09516741B2

    公开(公告)日：2016-12-06

    申请号：US14911707

    申请日：2014-08-12

    Applicant: Denka Company Limited

    Inventor： Hideki Hirotsuru ,  Shuhei Nonaka ,  Toshikatsu Mitsunaga ,  Koki Ikarashi ,  Kouji Miyata ,  Taiki Nishi ,  Saori Inoue ,  Fumiya Kobayashi

    IPC: H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  C08K7/00 ,  H05K3/02 ,  H05K3/38 ,  C08K3/38

    CPC classification number: H05K1/0271 ,  C08K7/00 ,  C08K2003/385 ,  C08K2201/004 ,  H05K1/0203 ,  H05K1/0306 ,  H05K1/0353 ,  H05K1/0373 ,  H05K1/09 ,  H05K3/022 ,  H05K3/38 ,  H05K2201/0104 ,  H05K2201/066

    Abstract: A boron nitride/resin composite circuit board having high heat dissipation characteristics and high reliability is provided. A boron nitride/resin composite circuit board, including: a plate-shaped resin-impregnated boron nitride sintered body having a plate thickness of 0.2 to 1.5 mm, the plate-shaped resin-impregnated boron nitride sintered body including 30 to 85 volume % of a boron nitride sintered body having boron nitride particles bonded three-dimensionally, the boron nitride particles having an average long diameter of 5 to 50 μm, and 70 to 15 volume % of a resin; and a metal circuit adhered onto both principal planes of the plate-shaped resin-impregnated boron nitride sintered body, the metal circuit being copper or aluminum, wherein: a ratio of a linear thermal expansion coefficient in a plane direction of the resin-impregnated boron nitride sintered body at 40 to 150° C. (CTE1) and a linear thermal expansion coefficient of the metal circuit at 40 to 150° C. (CTE2) (CTE1/CTE2) is 0.5 to 2.0.

    Abstract translation: 提供具有高散热特性和高可靠性的氮化硼/树脂复合电路板。 一种氮化硼/树脂复合电路板，包括：板厚为0.2〜1.5mm的板状树脂浸渍氮化硼烧结体，含有30〜85体积％的板状树脂浸渍氮化硼烧结体 具有三维结合的氮化硼颗粒的氮化硼烧结体，平均长径为5〜50μm的氮化硼颗粒和70〜15体积％的树脂; 以及附着在板状树脂浸渍氮化硼烧结体的两个主平面上的金属电路，金属电路为铜或铝，其中：树脂浸渍硼的平面方向的线性热膨胀系数的比例 40℃〜150℃（CTE1）的金属电路的线性热膨胀系数（CTE2）（CTE1 / CTE2）为40〜150℃。

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