公开(公告)号：EP4415051A1

公开(公告)日：2024-08-14

申请号：EP23205387.6

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： HEBERT, Francois

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/66068 ,  H01L29/1608 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/0696 ,  H01L21/047

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the first trench, the first doped region. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.

公开(公告)号：EP4404245A3

公开(公告)日：2024-08-07

申请号：EP23202561.9

申请日：2023-10-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： RAGHUNATHAN, Uppili S. ,  JAIN, Vibhor ,  NGU, Yves T. ,  KANTAROVSKY, Johnatan A. ,  VENTRONE, Sebastian T.

IPC: H01L21/331 ,  H01L23/34 ,  H01L29/73 ,  H01L29/737 ,  H01L21/324 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L29/7302 ,  H01L29/0821 ,  H01L29/66242 ,  H01L21/324 ,  H01L23/34 ,  H01L29/0649

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.

公开(公告)号：EP4401124A1

公开(公告)日：2024-07-17

申请号：EP23202558.5

申请日：2023-10-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： LEVY, Mark D. ,  CUCCI, Brett T. ,  PORTER, Spencer H. ,  SHARMA, Santosh

IPC: H01L23/00 ,  H01L23/58 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L23/564 ,  H01L23/585 ,  H01L29/7786 ,  H01L29/2003 ,  H01L29/1066

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures and methods of manufacture. The structure includes: a semiconductor substrate; a channel layer above the semiconductor substrate; a trench within the channel layer, extending to the semiconductor substrate; and a moisture barrier layer lining sidewalls and a bottom surface of the trench.

公开(公告)号：EP4400885A1

公开(公告)日：2024-07-17

申请号：EP23195594.9

申请日：2023-09-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Wu, Zhuojie

IPC: G02B6/36 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L23/562 ,  H01L23/585 ,  G02B6/4228 ,  G02B6/4202

Abstract: A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.

公开(公告)号：EP4400880A1

公开(公告)日：2024-07-17

申请号：EP23204229.1

申请日：2023-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng

IPC: G02B6/122 ,  G02B6/124

CPC classification number: G02B6/1228 ,  G02B6/124 ,  G02B6/12002 ,  G02B6/12016 ,  G02B6/12007

Abstract: Structures for an optical component, such as an optical reflector or an Echelle grating, and methods of forming such structures. The structure comprises a first waveguide core positioned in a vertical direction over a semiconductor substrate. The first waveguide core includes a tapered section and a plurality of segments separated by a plurality of gaps. A second waveguide core, which is positioned in the vertical direction relative to the first waveguide core, includes a portion positioned adjacent to the first waveguide core.

公开(公告)号：EP4398299A1

公开(公告)日：2024-07-10

申请号：EP23195592.3

申请日：2023-09-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mazza, James P. ,  Zeng, Jia ,  Zhu, Xuelian ,  Jain, Navneet K. ,  Rashed, Mahbub ,  Mazza, Jacob

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L2027/1187520130101 ,  G06F30/392 ,  H01L2027/1188120130101

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：EP4386755A1

公开(公告)日：2024-06-19

申请号：EP23197838.8

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Parvarandeh, Pirooz ,  Gopinath, Venkatesh P. ,  Jain, Navneet ,  Paul, Bipul C. ,  Mulaosmanovic, Halid

IPC: G11C14/00

CPC classification number: G11C14/0072

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：EP4386455A1

公开(公告)日：2024-06-19

申请号：EP23204238.2

申请日：2023-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： SRIVASTAVA, Ravi Prakash ,  BIAN, Yusheng ,  PANDEY, Shesh Mani ,  JAIN, Vibhor

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/136 ,  G02B2006/1209720130101 ,  G02B6/1223

Abstract: Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure comprises a substrate, a dielectric layer over the substrate, and a waveguide core over the substrate. The structure further comprises an airgap that extends at least partially through the dielectric layer and that surrounds a plurality of sides of a portion of the waveguide core.

公开(公告)号：EP4382976A1

公开(公告)日：2024-06-12

申请号：EP23199265.2

申请日：2023-09-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： DASGUPTA, Arpan ,  ROBSON, Norman W. ,  MOY, Danny

IPC: G02B6/13

CPC classification number: G02B2006/1210720130101 ,  G02B6/13 ,  G02B2006/1214720130101

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an identification system, method of manufacture and method of use. The structure includes at least one waveguide structure and at least one damaged region positioned in a unique pattern on the at least one waveguide structure.

公开(公告)号：EP4376092A1

公开(公告)日：2024-05-29

申请号：EP23201745.9

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Lydon-Nuhfer, Megan ,  Shank, Steven M. ,  Vallett, Aaron L. ,  Abou-Khalil, Michel ,  McTaggart, Sarah A. ,  Krishnasamy, Rajendran

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/045 ,  H01L21/30608 ,  H01L29/66621

Abstract: An integrated circuit (IC) structure includes a V-shaped cavity in a semiconductor substrate. A source region and a drain region are on opposing sides of the V-shaped cavity. A gate structure includes a gate dielectric layer, spacers, and a gate electrode on the gate dielectric layer between the spacers. The gate structure is fully within the V-shaped cavity. The IC structure provides a switch that finds advantageous application as part of a low noise amplifier. The IC structure provides a smaller gate width, decreased capacitance, increased gain and increased radio frequency (RF) performance compared to planar devices or devices without the gate structure fully within V-shaped cavity.