公开(公告)号：EP0811988A1

公开(公告)日：1997-12-10

申请号：EP96830326.3

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G11C29/12 ,  G06F11/006

Abstract: A semiconductor memory device comprising: at least one output data terminal (OB1-OB16,I/O1-I/O16); a matrix of memory cells comprising a plurality of columns (BL) of memory cells; multiplexer means (12) associated to said matrix of memory cells for selectively coupling one of said columns to respective sensing means (13) driving said output data terminal; redundancy columns (RBL) of redundancy memory cells for functionally replacing defective columns in said matrix; first means (RR1-RR4,1) for storing defective addresses of said defective columns in said matrix, for comparing said defective addresses with a current address supplied to the memory device and for selecting a redundancy column when the current address coincides with one of said defective addresses; means for generating an internal timing signal (ATD) activated upon changing of a current address (ADD) supplied to the memory device, the internal timing signal (ATD) remaining activated for a prescribed time starting from the beginning of a read cycle of the memory device. The memory device comprises: redundancy sensing means (10) associated to said redundancy columns (RBL), and redundancy control means (2,3,8,9) supplied by the internal timing signal (ATD) for coupling said output data terminal (OB1-OB16,I/O1-I/O16) of the memory device to said redundancy sensing means (10) in alternative to said sensing means (13) when the current address supplied to the memory device is a defective address, said redundancy control means maintaining the output data terminal of the memory device coupled to said sensing means (13) independently of the current address being a defective address as long as the internal timing signal (ATD) is activated.

Abstract translation: 一种半导体存储器件，包括：至少一个输出数据端子（OB1-OB16，I / O1-I / O16）; 包括存储器单元的多个列（BL）的存储器单元的矩阵; 与所述存储器单元矩阵相关联的多路复用器装置（12），用于选择性地将所述列中的一个耦合到驱动所述输出数据端的相应感测装置（13） 冗余存储单元的冗余列（RBL），用于功能地替换所述矩阵中的有缺陷的列; 用于在所述矩阵中存储所述缺陷列的缺陷地址的第一装置（RR1-RR4,1），用于将所述缺陷地址与提供给存储装置的当前地址进行比较，以及当当前地址与所述存储装置之一一致时选择冗余列 有缺陷的地址; 用于产生在提供给存储装置的当前地址（ADD）改变时激活的内部定时信号（ATD）的装置，从存储器的读取周期的开始开始的规定时间内保持激活的内部定时信号（ATD） 设备。 存储器件包括：与所述冗余列（RBL）相关联的冗余感测装置（10）和由内部定时信号（ATD）提供的冗余控制装置（2,3,8,9），用于将所述输出数据终端 当提供给存储装置的当前地址是缺陷地址时，存储装置的所述冗余感测装置（10）的所述冗余感测装置（10）替代所述感测装置（13），所述冗余度控制装置 只要内部定时信号（ATD）被激活，维持与所述感测装置（13）相连接的存储装置的输出数据终端，独立于作为缺陷地址的当前地址。

公开(公告)号：EP0811986A1

公开(公告)日：1997-12-10

申请号：EP96830318.0

申请日：1996-06-05

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Calligaro, Cristiano ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Cappelletti, Paolo ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5634

Abstract: A page-mode semiconductor memory device comprises a matrix (1) of memory cells (MC') arranged in rows (R) and columns (C), each row (R) forming a memory page (MP1-MPn) of the memory device and comprising at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC'), memory page selection means (2) for selecting a row (R) of the matrix (1), and a plurality of sensing circuits (3') each one associated to a respective column (C) of the matrix. The memory cells (MC') are multiple-level memory cells which can be programmed in a plurality of c=2 b (b>1) programming states to store b information bits, and the sensing circuits (3') are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells (MC'), at each step one of said b information bits being determined, said at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC') of a row (R) forming a number b of memory words of a memory page (MP1-MPn).

Abstract translation: 页模式半导体存储器件包括以行（R）和列（C）排列的存储单元（MC'）的矩阵（1），每行（R）形成存储器件的存储器页（MP1-MPn） 并且包括用于选择矩阵（1）的行（R）的至少一个组（MW1，MW2-MW2m-1，MW2m）的存储器单元（MC'），存储器页选择装置（2） 每个检测电路（3'）与矩阵的相应列（C）相关联。 存储单元（MC'）是可以以多个c = 2（b> 1）编程状态编程的多级存储器单元，用于存储b个信息位，并且感测电路（3'）是串行 所述至少一个组（MW1）包括：在所述b个信息比特中的每个步骤中确定所述b个信息比特中的每个步骤中存储的存储单元（MC'）中的b个信息比特， ，MW2-MW2m-1，MW2m）形成存储器页（MP1-MPn）的存储器字数b的行（R）的存储器单元（MC'）。

公开(公告)号：EP0811918A1

公开(公告)日：1997-12-10

申请号：EP96830324.8

申请日：1996-06-06

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: A semiconductor memory device comprises: a plurality of output data terminals (I/OB1-I/OB16,I/O1-I/O16); a matrix of memory cells comprising a plurality of groups (P) of columns (BL) of memory cells, each group of columns being associated to a respective output data terminal; column selection means (4) associated to the matrix of memory cells for selectively coupling one column (BL) for each of the group (P) of columns to a respective sensing means (5) driving the output data terminal; redundancy columns (RBL) of redundancy memory cells for functionally replacing defective columns in the matrix; redundancy column selection means (1) associated to the redundancy columns (RBL) for selectively coupling one redundancy column to a redundancy sensing means (11); defective address storage means (RR,2) for storing defective addresses of the defective columns and identifying codes (OC0-OC3) suitable for identifying the groups (P) of columns wherein the defective columns are located, for comparing the defective addresses with a current address (CADD) supplied to the memory device and for driving the redundancy column selection means for selecting a redundancy column when a current address supplied to the memory device coincides with one of the defective addresses. A shared bus (INTBUS) including a plurality of signal lines (INTBUSi) is provided in the memory device for interconnecting a plurality of circuit blocks (100) of the memory device and for transferring signals between the circuit blocks, the shared bus (INTBUS) being selectively assignable to the circuit blocks in prescribed respective time intervals. The memory device also comprises first bus assignment means (3) associated to the defective address storage means (RR) and second bus assignment means (8) associated to the sensing means (5). The first bus assignment means (3) assign the shared bus (INTBUS), during a first prescribed time interval of a read cycle of the memory device, to the defective address storage means (RR,2) for transferring the identifying code (OC0-OC3) of an addressed defective column to the output data terminals; the second bus assignment means (8) assign the shared bus (INTBUS), during a second prescribed time interval of the read cycle, to the sensing means (5) for transferring output signals of the sensing means (5) to the output data terminals. The transferred identifying code determining an output data terminal associated to the group (P) of columns to which the addressed defective column belongs to be supplied by an output signal of the redundancy sensing means (11) in alternative to an output of the sensing means (5) associated to the group (P) of columns.

Abstract translation: 半导体存储器件包括：多个输出数据端子（I / OB1-I / OB16，I / O1-I / O16）; 包括存储器单元的列（BL）的多个组（P）的存储器单元的矩阵，每组列与相应的输出数据端相关联; 列选择装置（4），其与存储器单元的矩阵相关联，用于选择性地将每个列（P）列的一列（BL）耦合到驱动输出数据端的相应感测装置（5） 冗余存储单元的冗余列（RBL），用于功能地替换矩阵中的有缺陷的列; 与冗余列（RBL）相关联的用于选择性地将一个冗余列耦合到冗余感测装置（11）的冗余列选择装置（1）; 用于存储缺陷列的缺陷地址的缺陷地址存储装置（RR，2）和适合于识别缺陷列所在的列的组（P）的识别代码（OC0-OC3），用于将缺陷地址与电流 提供给存储装置的地址（CADD）和用于驱动冗余列选择装置，用于当提供给存储装置的当前地址与缺陷地址之一重合时选择冗余列。 包括多条信号线（INTBUSi）的共享总线（INTBUS）被提供在存储器件中，用于互连存储器件的多个电路块（100），并用于在电路块之间传送信号，共享总线（INTBUS） 可以在规定的各个时间间隔内选择性地分配给电路块。 存储装置还包括与缺陷地址存储装置（RR）相关联的第一总线分配装置（3）和与感测装置（5）相关联的第二总线分配装置（8）。 第一总线分配装置（3）在存储装置的读取周期的第一规定时间间隔内将共享总线（INTBUS）分配给用于传送识别码（OC0- OC3）到输出数据终端; 第二总线分配装置（8）在读周期的第二规定时间间隔期间将共享总线（INTBUS）分配给感测装置（5），用于将感测装置（5）的输出信号传送到输出数据端 。 所传送的识别码确定与寻址的缺陷列属于的列的组（P）相关联的输出数据终端由冗余感测装置（11）的输出信号提供，以代替感测装置的输出（ 5）与列（P）组相关联。

公开(公告)号：EP0809254A1

公开(公告)日：1997-11-26

申请号：EP96830299.2

申请日：1996-05-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Commodaro, Stefano

IPC: G11C16/06

CPC classification number: G11C8/10 ,  G11C16/12

Abstract: The row decoder includes a predecoding stage (203) supplied with row addresses and generating predecoding signals; and a final decoding stage (204), which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage (203) includes a number of predecoding circuits (15) presenting two parallel signal paths: a low-voltage path (30) used in read mode, and a high-voltage path (31) used in programming mode. A CMOS switch (32) separates the two paths, is driven by high voltage via a voltage shifter (45) in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract translation: 行解码器包括提供行地址并产生预解码信号的预解码级（203） 以及最终解码级（204），其基于预解码信号驱动阵列中的各行。 预解码级（203）包括多个预解码电路（15），其呈现两个并行信号路径：在读取模式下使用的低电压路径（30）和在编程模式下使用的高压路径（31）。 CMOS开关（32）在编程模式下通过电压转换器（45）以高电压驱动两路，并且以预解码级形成，不涉及集成问题。

公开(公告)号：EP0557253B1

公开(公告)日：1997-11-19

申请号：EP93830047.2

申请日：1993-02-11

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Contiero, Claudio ,  Galbiati, Maria Paola ,  Zullino, Lucia

IPC: H01L29/772 ,  H01L29/08

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S148/053 ,  Y10S148/126

公开(公告)号：EP0806771A1

公开(公告)日：1997-11-12

申请号：EP96830243.0

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Maccarrone, Marco ,  Ghezzi, Stefano ,  Branchetti, Maurizio

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0433

Abstract: The present invention concerns a redundant UPROM cell (1) incorporating at least one memory element (P0) of the EPROM or flash type having a control terminal (CG) and a conduction terminal (X) to be biased, a register (2) with inverters connected to the memory element and MOS transistors (M1,M3) connecting said memory element (P0) with a reference low voltage power supply (Vdd). There is provided a precharge network (5) for the conduction terminal (X) of the flash cell and said network (5) incorporates a complementary pair of transistors (M4,M5). The second transistor (M5) of said pair (M4,M5) is a natural N-channel MOS type.
With the UPROM cell (1) is associated a circuit portion (10) for generating at output (U) a live signal (UPCH) to be applied to the control terminal of the second transistor (M5) with the portion (10) comprising a timing section (7) and a generation section (8) for said second live signal (UPCH).

Abstract translation: 本发明涉及一种冗余UPROM单元（1），其结合有EPROM或闪存类型的至少一个存储元件（P0），其具有控制端（CG）和要偏置的导通端（X），寄存器（2）具有 连接到存储元件的反相器和将所述存储元件（P0）与参考低电压电源（Vdd）连接的MOS晶体管（M1，M3）。 提供了一种用于闪存单元的导电端子（X）的预充电网络（5），并且所述网络（5）包含互补的一对晶体管（M4，M5）。 所述对（M4，M5）的第二晶体管（M5）是自然的N沟道MOS型。 与UPROM单元（1）相关联的电路部分（10）用于在输出（U）上产生要施加到第二晶体管（M5）的控制端的实时信号（UPCH），其中部分（10）包括 定时部分（7）和用于所述第二实时信号（UPCH）的生成部分（8）。

公开(公告)号：EP0805553A1

公开(公告)日：1997-11-05

申请号：EP96830255.4

申请日：1996-05-02

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Cusinato, Paolo ,  Bruccoleri, Melchiorre

IPC: H03K3/03 ,  H03L7/099

CPC classification number: H03K3/013 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/183

Abstract: Voltage-controlled oscillator, with high noise rejection of the supply voltage, of the type constituted by a plurality of delay cells (21, 22, 23) in an odd number N ≥3, which are connected to form a first ring oscillator (27, 34) and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR, comprising at least one second ring oscillator (28, 46) formed by a plurality of delay cells (23, 24, 25) in an odd number M ≥3, at least one of which is also a delay cell of the first oscillator (27, 34) and at least two of which (24, 25) do not belong to the first oscillator, at least one of these two cells (24, 25) being powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

Abstract translation: 由奇数N≥3的多个延迟单元（21,22,23）构成的类型的具有高电源电压噪声抑制的压控振荡器，连接形成第一环形振荡器（27 ，34），并且由供电电压Vcc和可变调节电压VR之间的差动供电，包括由奇数的多个延迟单元（23,24,25）形成的至少一个第二环形振荡器（28,46） M≥3，其中至少一个也是第一振荡器（27,34）的延迟单元，并且其中至少两个（24,25）不属于第一振荡器，这两个单元中的至少一个（ 24,25）以恒定电压（Vcc）供电，使得两个振荡器以相同的频率工作，并且两个振荡器之间的相互作用引入了具有有效降低噪声的效果的高频负反馈 的电源电压Vcc。

公开(公告)号：EP0805456A1

公开(公告)日：1997-11-05

申请号：EP96830242.2

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Maccarrone, Marco ,  Mulatti, Jacopo ,  Golla, Carla Maria

IPC: G11C11/00 ,  G11C16/06

CPC classification number: G11C16/30

Abstract: A circuit (1) for generating biasing signals in reading of a redundant UPROM cell (2) incorporating at least one memory element (FC) of the EPROM or flash type and having a control terminal (GC) and a conduction terminal (DC) to be biased as well as MOS transistors (M1,M2) connecting said memory element (FC) with a reference low supply voltage (Vcc) comprises a voltage booster (3) for generating at output (U1) a first voltage signal (UGV) to be applied to the control terminal (GC) of the memory element (FC) and a limitation network (5) for said voltage signal (UGV) connected to the output (U1) of the voltage booster (3).
There is also provided a circuit portion (10) for generating at output (U2) a second voltage signal (Vb) to be applied to the control terminal of one (M2) of the above mentioned transistors (M1,M2). This circuit portion (10) comprises a timing section (7) interlocked with the voltage booster (3) of a section (8) generating the second voltage signal (Vb).

Abstract translation: 一种用于在读入包括EPROM或闪存类型的至少一个存储元件（FC）并且具有控制端（GC）和导通端（DC）的冗余UPROM单元（2）的电路中产生偏置信号的电路（1） 连接所述存储元件（FC）与参考低电源电压（Vcc）的MOS晶体管（M1，M2）包括用于在输出（U1）处产生第一电压信号（UGV）至 施加到存储元件（FC）的控制端子（GC）和用于连接到升压器（3）的输出端（U1）的所述电压信号（UGV）的限制网络（5）。 还提供了一个电路部分（10），用于在输出端（U2）产生要施加到一个（M2）上述晶体管（M1，M2）的控制端的第二电压信号（Vb）。 该电路部分（10）包括与产生第二电压信号（Vb）的部分（8）的升压器（3）互锁的定时部分（7）。

公开(公告)号：EP0805454A1

公开(公告)日：1997-11-05

申请号：EP96830246.3

申请日：1996-04-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Dallabora, Marco ,  Villa, Corrado ,  Ghilardelli, Andrea

IPC: G11C7/00 ,  G11C16/06

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

Abstract: The invention relates to a sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a matrix of electrically programmable and erasable cells, the circuit comprising a sense amplifier which has a first input connected to a reference load column (5) incorporating a reference cell, and a second input connected to a second, matrix load column (6) incorporating a cell of the memory matrix (11). The circuit comprises a small matrix (12) of reference cells connected, in parallel with one another, in the reference column (5).
Also provided is a double current mirror (20) having a first mirror column (15) which is connected to a node (A) in the load column (5) connected to the first input, and a second mirror column (16) coupled to the second load column (6) to locally replicate, on the second mirror column (16), the electric potential at said node (A) during the load equalizing step.

Abstract translation: 本发明涉及一种用于读取和验证包括电可编程和可擦除单元的矩阵的半导体集成器件中的非易失性存储器单元的内容的读出放大器电路，该电路包括读出放大器，该读出放大器具有连接到参考的第一输入 加载列（5）和参考单元的第二输入，以及连接到结合有存储矩阵（11）的单元的第二矩阵加载列（6）的第二输入。 电路包括在参考柱（5）中彼此并联连接的参考单元的小矩阵（12）。 还提供了一种双电流镜（20），其具有连接到连接到第一输入的负载列（5）中的节点（A）的第一反射镜柱（15）和与第一反射镜 所述第二加载列（6）在所述第二反射镜列（16）处在所述负载均衡步骤期间在所述节点（A）处局部复制所述电位。

公开(公告)号：EP0661756B1

公开(公告)日：1997-10-29

申请号：EP93830538.0

申请日：1993-12-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan ,  Sabatini, Marco

IPC: H01L29/788 ,  H01L29/10 ,  G11C27/00

CPC classification number: H01L29/7881 ,  H01L29/1033