公开(公告)号：US20250007630A1

公开(公告)日：2025-01-02

申请号：US18344116

申请日：2023-06-29

Applicant: Silicon Laboratories Inc.

Inventor： Sriram Mudulodu ,  Manoj Kumar Medam

IPC: H04B17/318 ,  H04L27/00

Abstract: In one embodiment, a receiver includes: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) analog signal comprising a packet; an analog-to-digital converter (ADC) coupled to the AFE circuit to receive and digitize an analog signal based on the RF analog signal into a digital signal; a packet detector coupled to the ADC to detect the packet based on the digital signal; and a computation circuit coupled to the packet detector. The computation circuit may be configured to determine a received signal strength indicator (RSSI) value based at least in part on a portion of a preamble of the packet.

公开(公告)号：US20240429926A1

公开(公告)日：2024-12-26

申请号：US18821040

申请日：2024-08-30

Applicant: Silicon Laboratories Inc.

Inventor： John M. Khoury ,  Michael Wu

IPC: H03L7/099 ,  H03B5/32

Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.

公开(公告)号：US12175118B2

公开(公告)日：2024-12-24

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US12146935B2

公开(公告)日：2024-11-19

申请号：US17893635

申请日：2022-08-23

Applicant: Silicon Laboratories Inc.

Inventor： Anant Verma

IPC: G01R35/00 ,  G01R21/06 ,  G01R31/26

Abstract: A system and method for performing production testing on high power semiconductor devices is disclosed. The system includes signal generators, RF meters, sockets, couplers and connectors which also function as switches when connected to an external cable. A calibration process is executed which allows the controller to create a correlation between measurements taken by the RF meter and the actual voltages, and power levels present at the device under test. By performing this calibration, it is possible to perform production testing of devices much more quickly and reliably.

公开(公告)号：US12111407B2

公开(公告)日：2024-10-08

申请号：US17024874

申请日：2020-09-18

Applicant: Silicon Laboratories Inc.

Inventor： Lauri Mikael Hintsala

IPC: G01S5/02 ,  G01S5/00 ,  G01S5/08 ,  H04L1/08 ,  H04W4/80 ,  H04W56/00 ,  H04W72/0446

CPC classification number: G01S5/0215 ,  G01S5/0018 ,  G01S5/021 ,  G01S5/08 ,  H04L1/08 ,  H04W56/001 ,  H04W72/0446 ,  H04W4/80

Abstract: A system having a locator device and a plurality of tag devices is disclosed. The locator device comprises an antenna array allowing it to determine an angle of arrival for incoming signals from each of the plurality of tag devices. The system also defines a sequence of time slots, where each time slot has a specific function. The sequence may start with a locator time slot, where the locator device transmits a packet that informs all of the tag devices that this is the start of the sequence. A sync slot follows the locator time slot, where new tag devices may transmit a sync request to the locator device. Upon receipt of a sync request, the locator device assigns the new tag device a tag slot. Following the sync slot are a plurality of tag slots, where each tag device transmits an AoA packet during its assigned tag slot.

公开(公告)号：US20240334400A1

公开(公告)日：2024-10-03

申请号：US18127189

申请日：2023-03-28

Applicant: Silicon Laboratories Inc.

Inventor： Karthik Gunturi ,  Sunit Pujari ,  Ravikiran Nemali

IPC: H04W72/0446 ,  H04L69/166 ,  H04W4/80

CPC classification number: H04W72/0446 ,  H04L69/166 ,  H04W4/80

Abstract: A system and method for reducing packet error rates for L2CAP PDUs with large payloads is disclosed. The Bluetooth device fragments the large payload in several packets in accordance with well known algorithms. However, prior to transmission, the Bluetooth device redistributes the payload among these packets to reduce the maximum payload that is transmitted in one packet. In one embodiment, the Optimum Slot Utilization algorithm is used to determine the number and types of packets to be used, as well as the payloads in each packet. Once this is determined, the Bluetooth device then redistributes the payload across these packets to reduce the size of the largest payload that is transmitted in any packet, while still maintaining the same number of packets.

公开(公告)号：US20240333569A1

公开(公告)日：2024-10-03

申请号：US18193668

申请日：2023-03-31

Applicant: Silicon Laboratories Inc.

Inventor： Fabrice Christophe Olivier PORTIER

IPC: H04L27/26

CPC classification number: H04L27/26025 ,  H04L27/2614

Abstract: In one aspect, an apparatus comprises: a radio frequency (RF) front end circuit to receive and process an RF signal comprising a packet, the RF front end circuit to output a digital signal comprising the packet; and a baseband circuit coupled to the RF front end circuit. The baseband circuit may comprise: a demodulator to receive the digital signal comprising a plurality of extended and modulated symbols and to: perform a plurality of operations on at least some of a first block of the plurality of extended and modulated symbols according to a reverse recipe of operations to obtain a processed first block of the plurality of extended and modulated symbols; aggregate the processed first block of the plurality of extended and modulated symbols into an aggregated symbol; and demodulate the aggregated symbol to obtain at least one soft value.

公开(公告)号：US20240333316A1

公开(公告)日：2024-10-03

申请号：US18322639

申请日：2023-05-24

Applicant: Silicon Laboratories Inc.

Inventor： Sriram Mudulodu ,  Manoj Kumar Medam ,  Rambabu Katla

IPC: H04B1/00 ,  H04B1/12

CPC classification number: H04B1/0028 ,  H04B1/12

Abstract: A receiver includes: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) signal comprising a packet; an analog-to-digital converter (ADC) to receive and digitize the processed incoming RF signal into a digital signal; a packet detector to detect the packet; an estimation circuit to determine a carrier frequency offset (CFO) estimate based at least in part on a preamble of the packet; an averager to determine a CFO average value for a plurality of packets communicated between a device pair combination of the receiver and a transmitter; and a compensation circuit to compensate for CFO between the device pair combination based at least in part on the CFO average value.

公开(公告)号：US12107588B2

公开(公告)日：2024-10-01

申请号：US18076058

申请日：2022-12-06

Applicant: Silicon Laboratories Inc.

Inventor： John M. Khoury ,  Michael Wu

IPC: H03L7/099 ,  H03B5/32

CPC classification number: H03L7/0991 ,  H03B5/32

Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.

公开(公告)号：US12106973B2

公开(公告)日：2024-10-01

申请号：US17513037

申请日：2021-10-28

Applicant: Silicon Laboratories Inc.

Inventor： Erwin Hendarto

IPC: H01L21/56 ,  B23K26/362 ,  B23K101/40 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L21/565 ,  B23K26/362 ,  H01L21/67075 ,  H01L23/3157 ,  H01L23/552 ,  H01L24/49 ,  B23K2101/40 ,  H01L2924/01047 ,  H01L2924/18165

Abstract: In one embodiment, a method includes: laser ablating an encapsulant of a semiconductor package, until a threshold amount of the encapsulant remains above one or more die of the semiconductor package; and providing at least one drop of acid onto a surface of the ablated semiconductor package to acid etch for a first time duration, to remove a remaining portion of the encapsulant above the one or more die, where after the acid etch, a die of interest is exposed and the silver bond wires of the semiconductor package are preserved.