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公开(公告)号：KR1020100002723A
公开(公告)日：2010-01-07
申请号：KR1020080062723
申请日：2008-06-30
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
Abstract: PURPOSE: A semiconductor package and a method for manufacturing the semiconductor package are provided to improve the electrical characteristics by controlling a power supply terminal and a ground terminal at the same time. CONSTITUTION: In a semiconductor package and a method for manufacturing the semiconductor package, an electrical device(130) has power supply terminals and ground terminals. A wiring pattern(120) is formed in the substrate. The wiring pattern has a common pattern electrically connecting at least one group of power supply terminals and ground terminals.
Abstract translation: 目的：提供一种用于制造半导体封装的半导体封装和方法，以通过同时控制电源端子和接地端子来改善电气特性。 构成：在半导体封装和半导体封装的制造方法中，电气设备（130）具有电源端子和接地端子。 在衬底中形成布线图案（120）。 布线图案具有电连接至少一组电源端子和接地端子的共同图案。
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公开(公告)号：KR1020090080429A
公开(公告)日：2009-07-24
申请号：KR1020080006355
申请日：2008-01-21
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H05K1/0277 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L2924/14 , H01L2924/181 , H05K1/111 , H05K1/189 , H05K2201/097 , H05K2201/09709 , H05K2201/10128 , H05K2201/10674 , Y02P70/611 , H01L2924/00
Abstract: A wiring substrate, a tape package having the same, and a display device are provided to secure a sufficient alignment margin for forming a junction with a bump of a semiconductor chip by improving a structure thereof. A wiring substrate(100) includes a base film(110), a plurality of first wirings(130), and a plurality of second wirings(140). The base film has a chip mounting region(120) in which a semiconductor chip is mounted. The first wirings have a first junction terminal(132) which is electrically connected to the semiconductor chip. The first junction terminal is extended from the chip mounting region along a first direction. The first junction terminal is extended along a second direction inclined to the first direction. The second wirings have a second junction terminal(142) which is electrically connected to the semiconductor chip. The second junction terminal is extended from the chip mounting region along the first direction. The second junction terminal is extended in the opposite direction to the second direction.
Abstract translation: 提供布线基板，具有该布线基板的带封装和显示装置，以通过改进其结构来确保用于与半导体芯片的凸点形成结的足够的取向余量。 布线基板（100）包括基膜（110），多个第一布线（130）和多个第二布线（140）。 基膜具有安装半导体芯片的芯片安装区域（120）。 第一配线具有与半导体芯片电连接的第一接线端子（132）。 第一接线端子沿着第一方向从芯片安装区域延伸。 第一结端子沿着与第一方向倾斜的第二方向延伸。 第二配线具有电连接到半导体芯片的第二接线端子（142）。 第二结端子沿着第一方向从芯片安装区域延伸。 第二连接端子沿与第二方向相反的方向延伸。
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公开(公告)号：KR100834441B1
公开(公告)日：2008-06-04
申请号：KR1020070003443
申请日：2007-01-11
Applicant: 삼성전자주식회사
Inventor： 김동한
IPC: H01L21/60
CPC classification number: H01L23/49572 , H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/0401 , H01L2224/05554 , H01L2224/0603 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/81194 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H05K1/111 , H05K2201/09409 , H05K2201/09709 , H05K2201/10674 , Y02P70/611 , H01L2924/00
Abstract: A semiconductor device and a package including the same are provided to enhance a yield by improving an alignment structure of bumps. A first bump stream(122a) including a plurality of first bumps is positioned at a first distance from an edge of a semiconductor element on an active surface of the semiconductor element. A second bump stream(122b) including a plurality of second bumps is positioned at a second distance from the edge of the semiconductor element on the active surface of the semiconductor element. The second distance is larger than the first distance. A third bump stream(122c) including a plurality of third bumps is positioned at a third distance from the edge of the semiconductor element on the active surface of the semiconductor element. The second bumps or the third bumps are intersected with each other at least twice between the first bumps.
Abstract translation: 提供半导体器件和包括该半导体器件的封装以通过改善凸块的对准结构来提高产量。 包括多个第一凸起的第一凸起流（122a）位于半导体元件的有源表面上的半导体元件的边缘的第一距离处。 包括多个第二凸起的第二凸起流（122b）定位在半导体元件的有源表面上距离半导体元件的边缘的第二距离处。 第二距离大于第一距离。 包括多个第三凸起的第三凸起流（122c）位于半导体元件的有源表面上的半导体元件的边缘的第三距离处。 第二凸起或第三凸起在第一凸块之间彼此相交至少两次。
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公开(公告)号：KR1020080046021A
公开(公告)日：2008-05-26
申请号：KR1020060115430
申请日：2006-11-21
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49572 , H01L24/16 , H01L24/73 , H01L24/81 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/13016 , H01L2224/13017 , H01L2224/13019 , H01L2224/13099 , H01L2224/13144 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/189 , H05K3/303 , H05K3/3436 , H05K2201/0367 , H05K2201/094 , H05K2201/09709 , H05K2201/10674 , H05K2201/10681 , H05K2203/167 , Y02P70/613 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A semiconductor chip having bumps with different heights and a semiconductor package including the same are provided to prevent misalignment defects and short defects by allowing three-dimensional connection of the semiconductor chip and circuit board when the bond pad has fine pitches. A semiconductor chip(200) comprises a plurality of bond pads(202A,202B,202C) formed on a surface of the semiconductor chip, and a plurality of bumps(204B,204C) having different heights on the bond pads. The bond pads are arranged in a plurality of rows, each row having different height.
Abstract translation: 提供具有不同高度的凸块的半导体芯片和包括该半导体封装件的半导体封装件，以便当接合焊盘具有细间距时，通过允许半导体芯片和电路板的三维连接来防止未对准缺陷和短缺陷。 半导体芯片（200）包括形成在半导体芯片的表面上的多个接合焊盘（202A，202B，202C）和在接合焊盘上具有不同高度的多个凸块（204B，204C）。 接合焊盘布置成多行，每行具有不同的高度。
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公开(公告)号：KR100763549B1
公开(公告)日：2007-10-04
申请号：KR1020060099112
申请日：2006-10-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/50 , H01L23/4985 , H01L24/06 , H01L24/41 , H01L2224/05554 , H01L2224/06154 , H01L2224/41175 , H01L2924/00014 , H01L2924/14 , H01L2224/37099
Abstract: A semiconductor package is provided to accurately contact probes with external connection pads by extending a pitch between the external connection pads. Plural external connection pads(120,122) are arranged on a semiconductor chip(110) in a first direction. Plural external connection leads(130,132) are electrically connected to the external connection pads, respectively. Plural power pads(124) are aligned on the semiconductor chip in a direction perpendicular to the first direction. One power lead(136) is electrically connected to the power pads. The power lead has a width larger than that of the external connection leads.
Abstract translation: 提供半导体封装以通过在外部连接焊盘之间延伸间距来与外部连接焊盘精确地接触探针。 多个外部连接焊盘（120,122）沿第一方向布置在半导体芯片（110）上。 多个外部连接引线（130,132）分别电连接到外部连接焊盘。 多个电源焊盘（124）在垂直于第一方向的方向上对齐在半导体芯片上。 一个电源引线（136）电连接到电源焊盘。 电源引线的宽度大于外部连接引线的宽度。
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Patent Agency Ranking
公开(公告)号：KR1020070064896A
公开(公告)日：2007-06-22
申请号：KR1020050125484
申请日：2005-12-19
Applicant: 삼성전자주식회사
Inventor： 김동한
IPC: H01L23/12
CPC classification number: H01L23/49838 , G02F1/13452 , H01L23/4985 , H01L23/50 , H01L24/06 , H01L24/16 , H01L2224/0401 , H01L2224/06155 , H01L2224/16225 , H01L2924/01079 , H01L2924/14 , H01L2924/15173 , H01L2924/18161 , H05K3/323 , H05K2201/10136 , H05K2201/10446
Abstract: A semiconductor chip is provided to embody a semiconductor chip with high integration and a semiconductor chip package using the same by decreasing the area of an interconnection for supplying power. A semiconductor chip includes a plurality of input pads(210a,210ab,210b) and a plurality of output pads(230). The input pads include a plurality of successive first input pads and a second input pad for supplying power to the semiconductor chip. The second input pad is separated from the first input pads by interposing at least one output pad. The second input pad and the first input pads can be disposed at mutually confronting edges of the semiconductor chip.
Abstract translation: 提供半导体芯片来实现高集成度的半导体芯片和通过减小用于供电的互连区域的半导体芯片封装。 半导体芯片包括多个输入焊盘（210a，210ab，210b）和多个输出焊盘（230）。 输入焊盘包括多个连续的第一输入焊盘和用于向半导体芯片供电的第二输入焊盘。 通过插入至少一个输出垫将第二输入焊盘与第一输入焊盘分离。 第二输入焊盘和第一输入焊盘可以设置在半导体芯片的相互面对的边缘处。
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公开(公告)号：KR100699823B1
公开(公告)日：2007-03-27
申请号：KR1020030054221
申请日：2003-08-05
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/13452 , H01L23/5387 , H01L2224/16 , H01L2924/07811 , H05K1/118 , H05K1/147 , H05K2201/068 , H05K2201/10681 , H01L2924/00
Abstract: 저가형 플랙서블 필름 패키지 모듈 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명은 플랙서블 필름 패키지 모듈의 테이프 필름이 폴리이미드 재질의 제1 절연기판과, 상기 제1 절연기판보다 값이 싼 제2 절연기판을 연결하여 사용하는 플랙서블 필름 패키지 및 그 제조방법을 제공한다.
TCP. CoF, 플랙서블 필름 패키지, 저가형.-
公开(公告)号：KR1020070009840A
公开(公告)日：2007-01-19
申请号：KR1020050063755
申请日：2005-07-14
Applicant: 삼성전자주식회사
CPC classification number: G06K19/077 , G06K19/07743 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H05K1/0286 , H01L2924/00014
Abstract: A universal PCB and a smart card using the same are provided to reduce a manufacturing cost by performing mass production of various kinds of smart cards. A universal PCB includes a substrate main body, an internal circuit pattern(300), an outer circuit pattern, and vias(400). An IC(Integrated Circuit) chip is mounted on the substrate main body. The internal circuit pattern(300) is formed on a plane which is opposite to the IC chip of the substrate main body. The internal circuit pattern(300) includes a plurality of internal connection pad groups having internal connection pads and internal connection lines. The internal connection pads which are located at different places are electrically connected to the chip pad although the chip pad position of the IC chip is changed. The internal connection line connects electrically the internal connection pads to each other. The external circuit pattern includes external contact pads which are formed on the opposite plane. The connection vias(400) penetrate the substrate main body so that one external contact pad and one internal connection pad are electrically connected to each other.
Abstract translation: 提供通用PCB和使用其的智能卡，以通过大量生产各种智能卡来降低制造成本。 通用PCB包括基板主体，内部电路图案（300），外部电路图案和通孔（400）。 IC（集成电路）芯片安装在基板主体上。 内部电路图案（300）形成在与基板主体的IC芯片相对的平面上。 内部电路图案（300）包括具有内部连接焊盘和内部连接线的多个内部连接焊盘组。 尽管IC芯片的芯片焊盘位置改变，但是位于不同位置的内部连接焊盘电连接到芯片焊盘。 内部连接线将内部连接焊盘彼此电连接。 外部电路图案包括形成在相对平面上的外部接触焊盘。 连接通孔（400）穿透基板主体，使得一个外部接触焊盘和一个内部连接焊盘彼此电连接。
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公开(公告)号：KR1020070008010A
公开(公告)日：2007-01-17
申请号：KR1020050062905
申请日：2005-07-12
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/13452 , H01L23/4985 , H05K3/361
Abstract: A tape carrier package for a flat display device is provided to significantly reduce the manufacturing cost, thereby improving the productivity, by forming metal wires through electroless-plating. A first metal wire(54) is formed on a base film(50) vertically to the extending direction of the base film, wherein the first metal wire is connected to an input part of a flat display device. A second metal wire(56) is formed on the base film in the same direction of the first metal wire, wherein the second metal wire is connected to an output part of the flat display device. A semiconductor chip(60) is electrically connected to the first and second metal wires. A sealing part(62) covers the first metal wire, the second metal wire, and the semiconductor chip. The first and second metal wires are electroless-plated.
Abstract translation: 提供一种用于平板显示装置的带载包装件，以通过化学镀形成金属线，显着降低制造成本，从而提高生产率。 第一金属线（54）形成在垂直于基膜的延伸方向的基膜（50）上，其中第一金属线连接到平板显示装置的输入部分。 在第一金属线的相同方向上的基底膜上形成第二金属线（56），其中第二金属线连接到平面显示装置的输出部分。 半导体芯片（60）电连接到第一和第二金属线。 密封部分（62）覆盖第一金属线，第二金属线和半导体芯片。 第一和第二金属线是无电镀的。
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公开(公告)号：KR100626380B1
公开(公告)日：2006-09-20
申请号：KR1020040054853
申请日：2004-07-14
Applicant: 삼성전자주식회사
IPC: H01L23/10
CPC classification number: H01L23/50 , H01L23/13 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 개시되는 반도체 패키지는 반도체 칩 및 배선 패턴이 형성된 기판이 놓여지는 금속판을 포함한다. 반도체 칩이 직접 금속판과 접촉하여 열적 특성이 향상되고 또한 기판이 금속판에 의해서 지지되어 패키지의 기계적 안정성을 높일 수 있다. 특히 본 발명의 반도체 패키지는 프로젝션 디스플레이 장치에 적용되는 DMD를 패키지 하는데 유용하게 적용될 수 있다.
반도체 패키지, DMD, PGA 패키지Abstract translation: 所公开的半导体封装包括其上放置有半导体芯片和其上形成有布线图案的基板的金属板。 半导体芯片直接接触金属板以改善热特性，并且衬底可由金属板支撑以增强封装的机械稳定性。 特别地，本发明的半导体封装可以有利地应用于封装应用于投影显示装置的DMD。
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