公开(公告)号：KR100368121B1

公开(公告)日：2003-03-26

申请号：KR1019950041913

申请日：1995-11-17

Applicant: 삼성전자주식회사

Inventor： 허철 ,  최상국 ,  김홍근 ,  김재환

IPC: H01L21/304

Abstract: PURPOSE: A cleaning and drying apparatus of a gas pipe for a semiconductor manufacturing equipment is provided to improve the efficiency of a cleaning and drying process by simultaneously cleaning and drying a plurality of gas pipes during the predetermined time. CONSTITUTION: An ultrasonic solution tank(30) is provided with a drain hole and capable of being filled with a cleaning solution. A main supply pipe(10) is located in the ultrasonic solution tank(30) and capable of receiving gas or the cleaning solution. A central supply part(50) is connected with the main supply pipe(10) for selectively supplying the gas and the cleaning solution to the main supply pipe(10). A plurality of ports are installed in the main supply pipe(10). At this time, the ports are connected with various-sized gas pipes by using a flexible tube for spraying the gas and the cleaning solution into the gas pipes, so that the gas pipes are capable of simultaneously being cleaned and dried.

公开(公告)号：KR1020020071169A

公开(公告)日：2002-09-12

申请号：KR1020010011142

申请日：2001-03-05

Applicant: 삼성전자주식회사

Inventor： 홍수진 ,  박문한 ,  구주선 ,  허진화 ,  김홍근 ,  홍은기

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: PURPOSE: A method of forming an insulation layer in trench isolation type semiconductor device is provided to fill isolation layer into a trench having a high aspect ratio without defects by using an SOG(Spin On glass) layer. CONSTITUTION: A trench etch mask pattern(13) is formed on a substrate(10) including a pad oxide layer(11). A trench for isolation is formed on the substrate(10) by etching the substrate(10). A thermal oxide layer(15) is formed on an inner wall of the trench. A silicon nitride liner(17) is laminated on the thermal oxide layer(15). An SOG layer is formed on the substrate(10). A curing process for the SOG layer is performed. An etch process for the cured SOG layer(211) is performed. A silicon oxide layer(31) is deposited on the substrate(10) by a CVD(Chemical Vapor Deposition) method. A trench isolation layer is formed by removing the silicon nitride layer and the pad oxide layer(11).

Abstract translation: 目的：提供一种在沟槽隔离型半导体器件中形成绝缘层的方法，通过使用SOG（旋转玻璃）层将隔离层填充到具有高纵横比的无沟槽的沟槽中。 构成：在包括衬垫氧化物层（11）的衬底（10）上形成沟槽蚀刻掩模图案（13）。 通过蚀刻基板（10）在基板（10）上形成用于隔离的沟槽。 在该沟槽的内壁上形成热氧化层（15）。 氮化硅衬垫（17）层压在热氧化物层（15）上。 在基板（10）上形成SOG层。 执行SOG层的固化过程。 执行固化的SOG层（211）的蚀刻工艺。 通过CVD（化学气相沉积）方法将氧化硅层（31）沉积在衬底（10）上。 通过去除氮化硅层和衬垫氧化物层（11）形成沟槽隔离层。

公开(公告)号：KR101934426B1

公开(公告)日：2019-01-03

申请号：KR1020120134532

申请日：2012-11-26

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  황광태 ,  고영민

IPC: H01L27/108 ,  H01L21/8242

公开(公告)号：KR1020170000894A

公开(公告)日：2017-01-04

申请号：KR1020150089889

申请日：2015-06-24

Applicant: 삼성전자주식회사

Inventor： 최윤석 ,  고영민 ,  김홍근 ,  이종명 ,  최병덕

IPC: H01L27/108

CPC classification number: H01L28/90 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852

Abstract: 반도체장치의제조방법은기판상에상부몰드막, 보잉방지막, 및상부지지막을차례로형성하는것, 건식식각공정을이용하여상기상부몰드막, 상기보잉방지막, 및상기상부지지막을관통하는스토리지노드홀을형성하는것, 상기스토리지노드홀 내에하부전극을형성하는것, 상기상부지지막및 상기보잉방지막을패터닝하여상기상부몰드막의일부를노출하는것, 제1 습식식각공정을이용하여상기상부몰드막및 상기보잉방지막을제거하는것, 및상기하부전극을덮는유전막및 상부전극을차례로형성하는것을포함한다. 상기건식식각공정에대하여, 상기보잉방지막은상기상부지지막과실질적으로동일한식각속도를갖는다. 상기제1 습식식각공정에대하여, 상기보잉방지막은상기상부지지막보다큰 식각속도를갖는다. 상기상부지지막의두께와상기보잉방지막의두께의합은상기스토리지노드홀의깊이의 15% 내지 25%이다.

Abstract translation: 一种半导体装置的制造方法，其特征在于，包括：通过干式蚀刻工序形成穿过上支撑层，弓形防止层和上模层的存储节点孔，在所述存储节点孔中形成下电极，使所述上支撑层 以及所述弯曲防止层，以暴露所述上模层的一部分，使用第一湿蚀刻工艺去除所述上模层和所述防弓层的至少一部分，并且顺序地形成覆盖所述上模具层的电介质层和上电极 下电极。 弯曲防止层的蚀刻速率可以基本上等于在干蚀刻工艺期间上支撑层的蚀刻速率。 在第一湿法蚀刻工艺期间，防弓层的蚀刻速率可高于上支撑层的蚀刻速率。

公开(公告)号：KR1020140070739A

公开(公告)日：2014-06-11

申请号：KR1020120134532

申请日：2012-11-26

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  황광태 ,  고영민

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/87 ,  H01L28/90

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate having a transistor, multiple lower electrodes which are formed on the substrate, a dielectric layer which is formed on the lower electrodes, a first supporting unit, and a second supporting unit, and an upper electrode which is formed on the dielectric layer. The first and the second supporting units are located between the lower electrodes. The first and the second supporting units include a first material and a second material.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括具有晶体管的基板，形成在基板上的多个下部电极，形成在下部电极上的电介质层，第一支撑单元和第二支撑单元，以及上部电极， 电介质层。 第一和第二支撑单元位于下电极之间。 第一和第二支撑单元包括第一材料和第二材料。

公开(公告)号：KR1020080006381A

公开(公告)日：2008-01-16

申请号：KR1020060065531

申请日：2006-07-12

Applicant: 삼성전자주식회사

Inventor： 최종완 ,  구주선 ,  김홍근 ,  최용순 ,  김성태 ,  백은경

IPC: H01L21/76 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11531 ,  H01L21/76838

Abstract: A device isolation film, a non-volatile memory device having the device isolation film, and a method for forming the device isolation layer and the memory device are provided to fill a trench by forming the device isolation film using a combination of a first HDP(High Density Plasma) oxide film, an SOG oxide film, and a second HDP oxide film. A gate insulation film(90) is formed on an active region on a substrate, which is defined by a trench on the substrate. A floating gate(100) is located on the gate insulation film. A device isolation SOG(Spin On Glass) oxide film(60r) is formed in the trench on the substrate. A seal oxide film is located in the trench on the substrate and fills in the SOG oxide film. The seal oxide film is recessed from an upper surface of the substrate. A blocking insulation film(110) is contacted with the floating gate and the seal oxide film. The blocking insulation film is arranged on a side surface of a substrate, which is exposed from an upper surface of the seal oxide film. A control gate electrode(120) is arranged on the blocking insulation film. A thickness of the seal oxide film is substantially the same at a side surface of the SOG oxide film and a sidewall of the trench.

Abstract translation: 提供了一种器件隔离膜，具有器件隔离膜的非易失性存储器件，以及用于形成器件隔离层和存储器件的方法，以通过使用第一HDP（ 高密度等离子体）氧化膜，SOG氧化物膜和第二HDP氧化物膜。 在由衬底上的沟槽限定的衬底上的有源区上形成栅极绝缘膜（90）。 浮栅（100）位于栅绝缘膜上。 在衬底上的沟槽中形成器件隔离SOG（旋转玻璃）氧化膜（60r）。 密封氧化膜位于衬底上的沟槽中并填充SOG氧化物膜。 密封氧化膜从基板的上表面凹陷。 阻挡绝缘膜（110）与浮动栅极和密封氧化膜接触。 阻挡绝缘膜布置在从密封氧化膜的上表面露出的基板的侧表面上。 控制栅极（120）布置在阻挡绝缘膜上。 密封氧化膜的厚度在SOG氧化物膜的侧面和沟槽的侧壁上基本相同。

公开(公告)号：KR1020070000062A

公开(公告)日：2007-01-02

申请号：KR1020050055499

申请日：2005-06-27

Applicant: 삼성전자주식회사

Inventor： 라상호 ,  나규태 ,  구주선 ,  김홍근

IPC: H01L21/76

Abstract: A method of filling an opening and a method of forming a trench isolation structure using the same are provided to increase density of a filler of the opening by using an expansible member formed on an inner surface of the opening. An opening(104) is formed by etching partially a substrate(100). An expansible member(106b) is formed on a sidewall of the opening. The expansible member is filled with a plurality of fillers(108a,108b). The volume of the expansible member is enlarged to increase the density of the fillers formed within the opening. The expansible member is formed with polysilicon. The volume of the expansible member is enlarged by performing a thermal oxidation process.

Abstract translation: 提供填充开口的方法和使用其形成沟槽隔离结构的方法，以通过使用形成在开口的内表面上的可膨胀构件来增加开口填料的密度。 通过部分地蚀刻衬底（100）形成开口（104）。 可膨胀构件（106b）形成在开口的侧壁上。 可膨胀构件填充有多个填料（108a，108b）。 可膨胀构件的体积被扩大以增加在开口内形成的填料的密度。 可膨胀构件由多晶硅形成。 通过进行热氧化处理来扩大可膨胀构件的体积。

公开(公告)号：KR100636031B1

公开(公告)日：2006-10-18

申请号：KR1020050058425

申请日：2005-06-30

Applicant: 삼성전자주식회사

Inventor： 김홍근 ,  나규태 ,  백은경 ,  구주선 ,  라상호

IPC: H01L21/8247

公开(公告)号：KR100522547B1

公开(公告)日：2005-10-19

申请号：KR1020030089305

申请日：2003-12-10

Applicant: 삼성전자주식회사

Inventor： 구주선 ,  홍은기 ,  김홍근 ,  나규태

IPC: H01L21/31

CPC classification number: H01L21/02164 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/316 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

Abstract: SOG를 사용한 층간 절연막 형성 방법이 개시되어 있다. 반도체 기판에서, 단차부를 이루는 구조물의 표면에 결합 촉진용 촉매 물질을 형성한다. 상기 결합 촉진용 촉매 물질 상에 SOG 물질을 코팅한다. 상기 SOG 물질을 열처리하여 실리콘 산화막을 형성한다. 상기 공정에 의하면, 고단차 영역을 보이드 없이 매립하면서도 하부 접착 특성 및 식각 내성이 우수한 층간 절연막을 형성할 수 있다.

公开(公告)号：KR1020050023981A

公开(公告)日：2005-03-10

申请号：KR1020030061771

申请日：2003-09-04

Applicant: 삼성전자주식회사

Inventor： 홍은기 ,  구주선 ,  김홍근 ,  나규태

IPC: H01L27/108

Abstract: PURPOSE: A method of forming a semiconductor device is provided to prevent the short between adjacent conductive patterns by using a self-aligning process. CONSTITUTION: At least two line patterns(115) composed of a conductive line(109) and a capping pattern(111) are arranged parallel with each other on a semiconductor substrate(101). An insulating spacer(117) is formed at both sidewalls of each line pattern. A mold layer(119a) is formed on the resultant structure by using a spin manner. A contact hole(125) for exposing partially the substrate to the outside is formed between the line patterns by patterning selectively the mold layer. The mold layer has a relatively high etch selectivity on the insulating spacer compared to a silicon oxide layer.

Abstract translation: 目的：提供一种形成半导体器件的方法，以通过使用自对准工艺来防止相邻导电图案之间的短路。 构成：由导线（109）和封盖图案（111）组成的至少两个线图案（115）在半导体衬底（101）上彼此平行地布置。 在每个线图案的两个侧壁处形成绝缘间隔物（117）。 通过旋转方式在所得结构上形成模具层（119a）。 通过图案选择性地形成模层，在线图案之间形成用于将衬底部分地暴露于外部的接触孔（125）。 与氧化硅层相比，模层具有相对高的绝缘间隔物的蚀刻选择性。