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公开(公告)号：KR101338158B1
公开(公告)日：2013-12-06
申请号：KR1020070071237
申请日：2007-07-16
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
Abstract: 비휘발성 기억 소자 및 그 형성 방법을 제공한다. 본 발명에 따르면, 전하 저장막과 기판 사이의 유전막의 프리 본드들(free bonds)을 감소시킨다. 이로써, 프리 본드들을 통한 전하들 누출 및/또는 프리 본드들에 전하들이 포획되는 것을 최소화할 수 있다. 그 결과, 비휘발성 기억 소자의 데이터 유지 특성 및/또는 내구성을 향상시킬 수 있다.
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公开(公告)号：KR1020090007977A
公开(公告)日：2009-01-21
申请号：KR1020070071237
申请日：2007-07-16
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833
Abstract: A nonvolatile memory element and a forming method thereof are provided to reduce free bonds of a dielectric layer, thereby improving durability and minimizing that charges are captured by the free bonds during elimination and/or writing operations. A dielectric layer(515) including a nitride film is formed on a substrate(500). A conversion operation is performed so that at least a part of the nitride film can include oxygen. A charge storage layer(520) is formed on the dielectric layer. A blocking insulation film(525) is formed on the charge storage layer. A gate electrode(530a) is formed on the blocking insulation film. The step that the conversion operation is performed so as for at least a part of the nitride film to include the oxygen is performed by oxidizing the nitride film. The nitride film is partly oxidized. The dielectric layer has at least two domains in which nitrogen concentration is remarkably high. The domain in which the nitrogen concentration is remarkably high comprises a first area(600), arranged in a border area between the oxide film and the substrate, and a second area(610) positioned within the oxide film.
Abstract translation: 提供非易失性存储元件及其形成方法以减少电介质层的自由键，从而提高耐久性，并在消除和/或写入操作期间通过游离键捕获电荷。 在基板（500）上形成包括氮化物膜的电介质层（515）。 进行转换操作，使得氮化物膜的至少一部分可以包括氧。 在电介质层上形成电荷存储层（520）。 在电荷存储层上形成阻挡绝缘膜（525）。 栅极电极（530a）形成在阻挡绝缘膜上。 通过氧化氮化物膜来进行转换操作以使至少一部分氮化膜包含氧的步骤。 氮化膜被部分氧化。 介电层具有至少两个其中氮浓度非常高的畴。 氮浓度非常高的区域包括布置在氧化物膜和衬底之间的边界区域中的第一区域（600）和位于氧化物膜内的第二区域（610）。
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公开(公告)号：KR100428783B1
公开(公告)日：2004-04-28
申请号：KR1020030056638
申请日：2003-08-14
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: An STI(Shallow Trench Isolation) type semiconductor device is provided to be capable of preventing damage of a silicon nitride liner. CONSTITUTION: A trench isolation layer is formed in a semiconductor substrate(10). The trench isolation layer is provided with a silicon nitride liner(15), a densified silicon oxide liner(17') and a gap-filling layer(23). At this time, the gap-filling layer(23) further includes the first gap-filling layer made of SOG(Spin On Glass) and the second gap-filling layer made of HDP(High Density Plasma) CVD oxide. Also, the densified silicon oxide liner(17') is an HTO(High Temperature Oxide) layer by densification at the temperature of 800°C.
Abstract translation: 目的：提供STI（浅沟槽隔离）型半导体器件以防止氮化硅衬垫的损坏。 构成：沟槽隔离层形成在半导体衬底（10）中。 沟槽隔离层设置有氮化硅衬垫（15），致密氧化硅衬垫（17'）和间隙填充层（23）。 此时，间隙填充层23还包括由SOG（旋涂玻璃）制成的第一间隙填充层和由HDP（高密度等离子体）CVD氧化物制成的第二间隙填充层。 而且，致密氧化硅衬里（17'）是通过在800和摄氏度的温度下致密化的HTO（高温氧化物）层。
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公开(公告)号：KR1020020072657A
公开(公告)日：2002-09-18
申请号：KR1020010012603
申请日：2001-03-12
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76224 , Y10S438/978
Abstract: PURPOSE: A trench isolation layer formed in a trench with high aspect ratio is provided to prevent a silicon nitride liner from being damaged when lower and upper parts of the trench are filled with different insulating materials. CONSTITUTION: The silicon nitride liner(15) is formed on a substrate(10) in which the trench for device isolation is formed by trench etching. As a protection layer, a silicon oxide liner(17) such as HTO is overlaid on the silicon nitride liner(15) by CVD. The silicon oxide liner(17) is then subjected to densification at high temperature of 800°C or more. Next, the first insulating material such as SOG is filled in the trench and partially removed by etching. When the first insulating material is etched from the upper part of the trench, the silicon oxide liner(17) prevents the damage of the silicon nitride liner(15). Next, the second insulating material(25) such as HDP CVD is filled in the upper part of the trench.
Abstract translation: 目的：提供形成在具有高纵横比的沟槽中的沟槽隔离层，以防止当沟槽的下部和上部被不同的绝缘材料填充时氮化硅衬垫被损坏。 构成：氮化硅衬垫（15）形成在衬底（10）上，其中通过沟槽蚀刻形成用于器件隔离的沟槽。 作为保护层，通过CVD将诸如HTO的氧化硅衬垫（17）通过CVD覆盖在氮化硅衬垫（15）上。 然后将氧化硅衬垫（17）在800℃或更高的高温下进行致密化。 接下来，将第一绝缘材料如SOG填充在沟槽中并通过蚀刻部分地去除。 当从沟槽的上部蚀刻第一绝缘材料时，氧化硅衬垫（17）防止氮化硅衬垫（15）的损坏。 接下来，诸如HDP CVD的第二绝缘材料（25）填充在沟槽的上部。
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公开(公告)号：KR1020160142743A
公开(公告)日：2016-12-13
申请号：KR1020150135555
申请日：2015-09-24
Applicant: 삼성전자주식회사
IPC: H01J37/32
Abstract: 본발명의기술적사상의일 실시예에의한아크방전장치는냉매유입구와냉매유출구가형성된하우징및 하우징에고정된투과부재를구비하는바디부및 하우징에장착되고, 서로대향하여배치된어노드전극및 캐소드전극을구비한전극부를포함할수 있다. 어노드전극은하우징과연결되는본체부및 본체부와결합되는어노드전극팁을구비하고, 어노드전극의내부에형성되는냉각라인은냉매유입구와냉매유출구와연결되고, 어노드전극팁의내벽과접하는것을특징으로한다.
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Patent Agency Ranking
公开(公告)号：KR1020060036712A
公开(公告)日：2006-05-02
申请号：KR1020040085787
申请日：2004-10-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L21/28273 , H01L21/823437
Abstract: 플래시 메모리 장치의 플로팅 게이트를 제조하는 방법에 있어서, 반도체 기판 상에 액티브 영역을 정의하며 상기 반도체 기판의 표면을 노출시키는 개구를 갖는 절연 패턴을 형성한다. 상기 절연 패턴이 형성된 반도체 기판을 세정한 후, 상기 반도체 기판을 수소 기체 분위기에서 열처리하고, 상기 액티브 영역 상에 실리콘 단결정층을 형성하며, 상기 실리콘 단결정층을 산화시켜 터널 산화막을 형성한다. 이때, 상기 터널 산화막 및 반도체 기판 사이의 계면성이 개선되어 상기 플래시 메모리의 문턱 전압을 일정하게 유지할 수 있다. 이어서, 상기 터널 산화막이 형성된 개구를 매립하는 폴리실리콘층을 형성하고, 상기 절연 패턴의 상부면이 노출되도록 평탄화 공정을 수행하여 상기 개구 내에 플로팅 게이트를 형성한다.
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公开(公告)号：KR1020040062298A
公开(公告)日：2004-07-07
申请号：KR1020030000101
申请日：2003-01-02
Applicant: 삼성전자주식회사
IPC: H01L21/762
Abstract: PURPOSE: A method for forming a trench structure of a semiconductor device is provided to form the trench structure by using a spin-on glass solution including perhydro silazene. CONSTITUTION: The first layer is formed on a substrate(10). The first layer pattern is formed by patterning the first layer. A field region of the substrate is exposed by forming the first layer pattern. A trench is formed on the substrate by etching the exposed part. An SOG layer for burying the trench is formed by coating an SOG solution including perhydro silazene on the substrate. The first layer pattern is exposed by planarizing the SOG layer. Ions are implanted into the SOG layer by using the first layer pattern as an ion mask. The SOG layer is formed as a silicon oxide layer(18a) by performing a thermal process for the substrate including the SOG layer. The first layer pattern is etched by using an etch ratio of the first layer pattern and the silicon oxide layer.
Abstract translation: 目的：提供一种用于形成半导体器件的沟槽结构的方法，以通过使用包括全氢硅氮烷的旋涂玻璃溶液形成沟槽结构。 构成：第一层形成在基底（10）上。 通过图案化第一层形成第一层图案。 通过形成第一层图案来暴露基板的场区域。 通过蚀刻暴露部分在衬底上形成沟槽。 通过在衬底上涂覆包括全氢硅氮烷的SOG溶液来形成用于掩埋沟槽的SOG层。 通过平坦化SOG层来暴露第一层图案。 通过使用第一层图案作为离子掩模将离子注入到SOG层中。 通过对包括SOG层的基板进行热处理，形成SOG层作为氧化硅层（18a）。 通过使用第一层图案和氧化硅层的蚀刻比来蚀刻第一层图案。
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公开(公告)号：KR100428806B1
公开(公告)日：2004-04-28
申请号：KR1020010039446
申请日：2001-07-03
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76224
Abstract: A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.
Abstract translation: 一种形成沟槽器件隔离结构的方法，其中，在半导体衬底的预定区域中形成沟槽之后，顺序形成下隔离图案，上衬里图案和上隔离图案以填充沟槽。 下部器件隔离层形成在半导体衬底的整个表面上，然后被蚀刻以形成下隔离图案，使得下隔离图案的顶表面低于半导体衬底的顶表面。 在包括下隔离图案的半导体衬底的整个表面上形成上衬里层和上器件隔离层，然后蚀刻以形成上衬里图案。 结果，上部衬里图案覆盖下部隔离图案的顶部表面并且围绕上部隔离图案的底部和侧壁。
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公开(公告)号：KR1020020071169A
公开(公告)日：2002-09-12
申请号：KR1020010011142
申请日：2001-03-05
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76224
Abstract: PURPOSE: A method of forming an insulation layer in trench isolation type semiconductor device is provided to fill isolation layer into a trench having a high aspect ratio without defects by using an SOG(Spin On glass) layer. CONSTITUTION: A trench etch mask pattern(13) is formed on a substrate(10) including a pad oxide layer(11). A trench for isolation is formed on the substrate(10) by etching the substrate(10). A thermal oxide layer(15) is formed on an inner wall of the trench. A silicon nitride liner(17) is laminated on the thermal oxide layer(15). An SOG layer is formed on the substrate(10). A curing process for the SOG layer is performed. An etch process for the cured SOG layer(211) is performed. A silicon oxide layer(31) is deposited on the substrate(10) by a CVD(Chemical Vapor Deposition) method. A trench isolation layer is formed by removing the silicon nitride layer and the pad oxide layer(11).
Abstract translation: 目的：提供一种在沟槽隔离型半导体器件中形成绝缘层的方法，通过使用SOG（旋转玻璃）层将隔离层填充到具有高纵横比的无沟槽的沟槽中。 构成：在包括衬垫氧化物层（11）的衬底（10）上形成沟槽蚀刻掩模图案（13）。 通过蚀刻基板（10）在基板（10）上形成用于隔离的沟槽。 在该沟槽的内壁上形成热氧化层（15）。 氮化硅衬垫（17）层压在热氧化物层（15）上。 在基板（10）上形成SOG层。 执行SOG层的固化过程。 执行固化的SOG层（211）的蚀刻工艺。 通过CVD（化学气相沉积）方法将氧化硅层（31）沉积在衬底（10）上。 通过去除氮化硅层和衬垫氧化物层（11）形成沟槽隔离层。
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公开(公告)号：KR101283574B1
公开(公告)日：2013-07-08
申请号：KR1020070080273
申请日：2007-08-09
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
Abstract: 2개의 질소 농도 피크를 가진 절연막을 형성하는 방법이 제공된다. 본 발명의 일 실시예에 의한 절연막을 형성하는 방법은, 기판 상에 절연막을 형성하고, 절연막에 제1 불순물을 열 공정을 이용하여 주입하여 하부 영역에 제1 불순물 농도 피크를 형성하고, 절연막에 제2 불순물을 열 공정을 이용하여 주입하여 상부 영역에 제2 불순물 농도 피크를 형성하는 것을 포함하고, 제1 불순물 농도 피크가 제2 불순물 농도 피크보다 높다.
플래시 메모리, 터널 절연막, 질소, 농도 피크
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