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    Decoding of LDPC code
    43.
    发明专利
    Decoding of LDPC code 未知

    公开(公告)号：GB2494577A

    公开(公告)日：2013-03-13

    申请号：GB201222466

    申请日：2011-05-25

    Applicant: IBM

    Inventor： ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAOYU ,  NGUYEN DUNG VIET

    IPC: G06F11/10 ,  G11C29/42 ,  H03M13/11

    Abstract: It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.

    Programming at least one multi-level phase change memory cell
    44.
    发明专利
    Programming at least one multi-level phase change memory cell 未知

    公开(公告)号：GB2492701A

    公开(公告)日：2013-01-09

    申请号：GB201218792

    申请日：2011-03-23

    Applicant: IBM

    Inventor： ELEFTHERIOU EVANGELOS ,  PANTAZI ANGELIKI ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  SEBASTIAN ABU

    IPC: G11C11/56 ,  G11C13/00

    Abstract: A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

    Method and apparatus for operating a storage device
    45.
    发明专利
    Method and apparatus for operating a storage device 未知

    公开(公告)号：GB2490828A

    公开(公告)日：2012-11-14

    申请号：GB201214600

    申请日：2011-01-27

    Applicant: IBM

    Inventor： ELEFTHERIOU EVANGELOS ,  HAEBERLE WALTER ,  JELITTO JENS ,  PANTAZI ANGELIKI

    IPC: G11B5/584

    Abstract: Method for operating a storage device with a tape (TP) and a head (HU) wherein the head (HU) comprises a first and a second read element (RE1, RE2). Each read element (RE1, RE2) is operable to detect servo-pattern of a particular servo band (SP). The first and the second read element (RE1, RE2) are arranged in such a way, that the tape (TP) at first passes one of both read elements (RE1, RE2) and subsequently passes the other of both read elements (RE1, RE2) when the tape (TP) moves in a predetermined longitudinal direction (X). A tape transport direction (TPDIR) of the tape (TP) along the longitudinal direction (X) is determined. The first read element (RE1) is selected dependent on the determined tape transport direction (TPDIR), when the determined tape transport direction (TPDIR) represents a direction where the tape (TP) at first passes the first read element (RE1) and subsequently the second read element (RE2). Otherwise the second read element (RE2) is selected. A position error signal (PES1) is determined dependent on the selected read element. With respect to a predetermined lateral reference point (REF) an estimated lateral track position (d est ) at a longitudinal position (x1) of the selected read element is estimated dependent on the determined position error signal (PES1). With respect to the predetermined reference point (REF) another estimated lateral track position (d* est ) at a longitudinal position (x2) of the non- selected read element is estimated in such a way that the other estimated lateral track position (d* est ) becomes a time-delayed representation of the estimated lateral track position (d est ).

    Solid-state storage system with parallel access of multiple flash/PCM devices
    47.
    发明专利
    Solid-state storage system with parallel access of multiple flash/PCM devices 未知

    公开(公告)号：GB2488057A

    公开(公告)日：2012-08-15

    申请号：GB201207470

    申请日：2010-11-26

    Applicant: IBM

    Inventor： ANTONAKOPOULOS THEODORE A ,  CIDECIYAN ROY D ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAO-YU ,  ILIADIS ILIAS

    IPC: G06F11/10 ,  G11C29/00

    Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

    48.
    发明专利
    未知

    公开(公告)号：AT479986T

    公开(公告)日：2010-09-15

    申请号：AT03732870

    申请日：2003-06-13

    Applicant: IBM

    Inventor： ANTONAKOPOULOS THEODORE ,  ELEFTHERIOU EVANGELOS ,  POZIDIS HARIS

    IPC: G11B20/12 ,  G11B20/14 ,  G11B9/14 ,  G11B20/10 ,  G11B27/30 ,  H03M5/14

    Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value {tilde over (x)}, where d is a predetermined number>=2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).

    49.
    发明专利
    未知

    公开(公告)号：AT421143T

    公开(公告)日：2009-01-15

    申请号：AT04731424

    申请日：2004-05-06

    Applicant: IBM

    Inventor： CIDECIYAN ROY ,  DHOLAKIA AJAY ,  ELEFTHERIOU EVANGELOS ,  MITTELHOLZER THOMAS

    IPC: G11B20/10 ,  G11B20/18

    Abstract: A method for decoding data in a data storage system includes generating an output bit stream; generating a first error corrected bit stream in dependence on the output bit stream; generating a second error corrected bit stream in dependence on the first error corrected bit stream; generating a checksum in dependence of the second error corrected bit stream; and, in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave: supplying data indicative of locations of correct bits in the second error corrected bit stream; and, regenerating the first error corrected bit stream in dependence on the pinning data.

    ADAPTIVE NOISE-PREDICTIVE PARTIAL-RESPONSE EQUALIZATION FOR CHANNELS WITH SPECTRAL NULLS
    50.
    发明专利
    ADAPTIVE NOISE-PREDICTIVE PARTIAL-RESPONSE EQUALIZATION FOR CHANNELS WITH SPECTRAL NULLS 未知

    公开(公告)号：CA2158014A1

    公开(公告)日：1994-12-22

    申请号：CA2158014

    申请日：1993-06-14

    Applicant: IBM

    Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

    IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10 ,  H04L25/03 ,  H04L25/497

    Abstract: The present application makes use of a novel adaptive noise-predictive parti al-response equalization scheme for channels (30) exhibiting spectral nulls and/or near nulls. The noise-predictive partial re sponse (PR) equalizer employed in the different embodime nts of the present invention consists of a linear PR equalizer (32) which shapes the channel response to a predetermined partial-respons e function, followed by a linear predictor. This scheme modifies the output se quence of said linear partial-response equalizer (32) by whitening the total distortion, i.e. by whitening the noise components and t he residual interference components at said linear PR eq ualizer output, thereby achieving the best possible signal-to-noise ratio (SNR) befo re detection.

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