公开(公告)号：JP2000164697A

公开(公告)日：2000-06-16

申请号：JP33676599

申请日：1999-11-26

Applicant: IBM ,  SIEMENS AG

Inventor： GARY B BRONER ,  COSTRINI GREG ,  RADENS CARL J ,  RAYNER E SCHNABEL

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To achieve low capacitance and low resistance by simultaneously performing the pattern formation of a via and a grooved line in an interlayer dielectric, by simultaneously etching the via and the grooved line, and by simultaneously filling the via and the grooved line with metal. SOLUTION: On a substrate, desired linear features and vertical interconnection are formed (S700). A grooved line and a via are simultaneously etched (S701). A metallization layer is subjected pattern formation by lithography, and is etched by RIE or the like (S702). The via and the grooved line are filled by the same metallization process (S703). The filled via and the grooved line are finished by one-time common etching or polishing process so that a structure has a flat and uniform upper surface (S704). As a result, both of low-capacitance and low-resistance metallization can be formed.

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：DE69939451D1

公开(公告)日：2008-10-16

申请号：DE69939451

申请日：1999-10-15

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory cell structure uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor. The buried strap connection between the trench capacitor and the bitline contact (CB) in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar (400) and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off- state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

公开(公告)号：DE60106256D1

公开(公告)日：2004-11-11

申请号：DE60106256

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

公开(公告)号：HK1042377A1

公开(公告)日：2002-08-09

申请号：HK02102046

申请日：2002-03-18

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J

IPC: H01L20060101 ,  H01L

公开(公告)号：DE69934357D1

公开(公告)日：2007-01-25

申请号：DE69934357

申请日：1999-06-17

Applicant: SIEMENS AG ,  IBM

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/8242 ,  H01L27/108

Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

公开(公告)号：DE102004025108A1

公开(公告)日：2005-03-10

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

公开(公告)号：DE10220542A1

公开(公告)日：2002-12-05

申请号：DE10220542

申请日：2002-05-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： RADENS CARL J ,  MANDELMAN JACK A ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.

公开(公告)号：SG70142A1

公开(公告)日：2000-01-25

申请号：SG1998005847

申请日：1998-12-16

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY PETER ,  MANDELMAN JACK ALLAN ,  RADENS CARL J ,  TONTI WILLIAM ROBERT PATRICK

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.