公开(公告)号：CA2453146C

公开(公告)日：2008-11-18

申请号：CA2453146

申请日：2002-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER

IPC: H03F3/45 ,  H04L25/02 ,  H04L25/20 ,  H04M1/00 ,  H04M3/00

Abstract: The invention relates to a line driver in which an input current (IINN) feeds a node (K1) which is connected to an input on an amplifier (OTA1). A further input on the amplifier (OTA1) has a reference voltage (VSGND) applied to it. The amplifier (OTA1) controls a current source (MN1) which outputs an output current (IOUTN). A current/voltage converter (R1) is connected between the node (K1) and the current source (MN1). A voltage/current converter (R2) is connected between the current source (MN1) and a ground (VSS).

公开(公告)号：DE10164971B4

公开(公告)日：2008-04-30

申请号：DE10164971

申请日：2001-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER

IPC: H03F3/45 ,  H04L25/02 ,  H04L25/20 ,  H04M1/00 ,  H04M3/00

公开(公告)号：DE102006009026A1

公开(公告)日：2007-08-30

申请号：DE102006009026

申请日：2006-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  SCHOENAUER TIM ,  GREGORIUS PETER ,  KEHRER DANIEL

IPC: G06F12/00

Abstract: The arrangement comprises an interface (4) for transferring data in the form of packets in accordance with pre-determined minutes, two memory banks (6) with a memory cell, and two memory bank access devices (1,2). The two packet processing devices (8) are present for coding or decoding the packets, where the different memory bank access devices are assigned to two packet processing devices.

公开(公告)号：DE102005051792A1

公开(公告)日：2007-05-03

申请号：DE102005051792

申请日：2005-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH ROLAND ,  GREGORIUS PETER

IPC: G06F12/00

Abstract: The method involves transmitting data between a memory control (200) and interface units (20), which are attached to memory modules (100a,100b,100c). The units (20) are arranged on same side of mechanically detachable connection (10) as the control. The data is transmitted between the units (20) and module over the connection. Clock signals assigned to the data signals are produced in the interface units by a phase servo loop (250). Independent claims are also included for the following: (1) a memory module for a memory device (2) a device for coupling memory module for data transmission to a memory control over the mechanically detachable connection (3) a memory device with the memory control, memory module and the device for coupling memory module for data transmission to a memory control over the mechanically detachable connection.

公开(公告)号：DE50208307D1

公开(公告)日：2006-11-16

申请号：DE50208307

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER

IPC: G05F3/00 ,  G05F1/575 ,  G05F3/26

公开(公告)号：DE102004037163B4

公开(公告)日：2006-08-17

申请号：DE102004037163

申请日：2004-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER

IPC: H03L7/081 ,  G11C11/4063

Abstract: A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.

公开(公告)号：DE102004055046A1

公开(公告)日：2006-05-24

申请号：DE102004055046

申请日：2004-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  SICHERT CHRISTIAN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  WALLNER PAUL

IPC: G11C7/00 ,  G11C11/407

Abstract: A semiconductor memory system has data transmission lines (DQ) connecting the interface circuits (1-4;5a, 5b) and via which the signal bursts of the write and read data signals of given burst lengths are transmitted from and to the memory control unit (20) and from and to the register unit (15a). The interface circuits are set up for transmission of the burst lengths at least of the write data expanded additional bits (ZB) together with at least each n-th signal burst. An independent claim is included for a method for transmission of write- read- data signals.

公开(公告)号：DE102004041331A1

公开(公告)日：2006-03-09

申请号：DE102004041331

申请日：2004-08-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  GREGORIUS PETER

IPC: G11C11/4072 ,  H03M7/00

Abstract: A code driver is described having a codeword source, which has n>1 source terminals and is designed to output at these terminals a sequence of n-digit codewords, each in the form of n parallel code characters, and having n parallel transmission paths between the n source terminals and n transmit terminals for sending the message represented by the codewords to a receiver. According to the invention, a selection device is provided, which indicates explicitly for each codeword which of the n digits of the codeword concerned are relevant to the decoding of the message in the receiver, and which, dependent on this explicit indication, activates only those of the n transmission paths that are assigned to the relevant digits of the codeword.

公开(公告)号：DE10337084A1

公开(公告)日：2005-03-17

申请号：DE10337084

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BONHAUS JOERG ,  DUDA THOMAS ,  GREGORIUS PETER ,  GAZSI LAJOS

IPC: H03C1/62 ,  H04B1/10 ,  H04B17/00 ,  H04L25/08 ,  H04L27/36 ,  H04L29/08

Abstract: Generator signals are generated by unit (10), providing signals with certain signal form determined in dependence on preset signal norm form. Matching unit (20) adapts generated signal form to properties of signal transmission channel. Signal generating and matching units are so fitted that signals transmitted, via transmission channel, from matching unit are in signal form corresponding to preset signal norm form. Signal matching and generating units are of digital type.

公开(公告)号：DE102004014451A1

公开(公告)日：2004-11-04

申请号：DE102004014451

申请日：2004-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  LINDT PAUL GEORG ,  MATTES HEINZ LUDWIG

IPC: G06F19/00 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C29/02

Abstract: The method involves starting the integrator after receiving start command from the memory buffer. The integrator is stopped, when the measurement pulse transmitted through signal line is detected by pulse detector, so that the integrated value of integrator indicates the delay time of signal lines (10,11), : An independent claim is also included for a memory buffer.