公开(公告)号：DE10345394A1

公开(公告)日：2005-05-19

申请号：DE10345394

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ ,  GUTSCHE MARTIN

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  B82B3/00

公开(公告)号：DE10202903A1

公开(公告)日：2003-08-14

申请号：DE10202903

申请日：2002-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ

IPC: G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/08

Abstract: A magnetoresistive tunnel element includes first and second electrodes and a tunnel barrier disposed between the two electrodes, the tunnel barrier having at least two barrier layers made of different barrier materials, the profile of a quantum mechanical barrier height within the tunnel barrier being asymmetrical and the conductivity of the tunnel element, therefore, being dependent on the polarity of a voltage Um between the two electrodes. Also provided is a magnetoresistive memory cell, a cell array of magnetoresistive memory cells, and a memory device having cell arrays.

公开(公告)号：DE10161312A1

公开(公告)日：2003-07-10

申请号：DE10161312

申请日：2001-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEINHOEGL WERNER ,  KREUPL FRANZ ,  HOENLEIN WOLFGANG

IPC: H01L21/768 ,  H01L51/30

Abstract: An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

公开(公告)号：DE10103340A1

公开(公告)日：2002-08-22

申请号：DE10103340

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ ,  HOENLEIN WOLFGANG

IPC: C01B31/02 ,  C23C16/02 ,  C23C16/26 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  B82B3/00 ,  B81C3/00 ,  D01F9/14 ,  H01L51/30 ,  H01L51/40

公开(公告)号：DE10006964C2

公开(公告)日：2002-01-31

申请号：DE10006964

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENLEIN WOLFGANG ,  ENGELHARDT MANFRED ,  KREUPL FRANZ

IPC: H01J9/02 ,  H01J1/304 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H05K3/40 ,  B82B3/00 ,  B82B1/00

Abstract: The invention provides in a preferred embodiment an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

公开(公告)号：DE10345393B4

公开(公告)日：2007-07-19

申请号：DE10345393

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ ,  SEIDEL ROBERT ,  PAMLER WERNER

IPC: H01L21/3205 ,  C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/44 ,  C23C16/455 ,  H01L21/283 ,  H01L21/8242

公开(公告)号：DE19860084B4

公开(公告)日：2005-12-22

申请号：DE19860084

申请日：1998-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  ENGELHARDT MANFRED ,  KREUPL FRANZ ,  SCHIELE MANUELA ,  SAENGER ANNETTE ,  HARTNER WALTER

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/304

公开(公告)号：DE102004023301A1

公开(公告)日：2005-12-15

申请号：DE102004023301

申请日：2004-05-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  KREUPL FRANZ ,  STEINLESBERGER GERNOT ,  KRETZ JOHANNES

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: The charge storage layer is designed such that electrical charge carriers can be introduced into or removed from it, selectively, by applying a given electrical potential to the bridge field effect transistor memory cell. An independent claim is included for the method of manufacture.

公开(公告)号：DE102004006544B3

公开(公告)日：2005-09-08

申请号：DE102004006544

申请日：2004-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KREUPL FRANZ ,  STEINLESBERGER GERNOT

IPC: H01L21/04 ,  H01L21/285 ,  H01L21/443 ,  H01L29/47 ,  H01L21/283 ,  H01L29/812

Abstract: The invention relates to a method for depositing a conductive carbon material ( 17 ) on a semiconductor ( 14 ) for forming a Schottky contact ( 16 ). The inventive method comprises the following steps: introducing a semiconductor ( 14 ) into a process chamber ( 10 ); heating the interior ( 10 ') of a process chamber ( 10 ) to a defined temperature; evacuating the process chamber ( 10 ) to a first defined pressure or below; heating the interior ( 10 ') of a process chamber ( 10 ) to a second defined temperature; introducing a gas ( 12 ) which comprises at least carbon, until a second defined pressure is achieved which is higher than the first defined pressure; and depositing the conductive carbon material ( 17 ) on the semiconductor ( 14 ) from the gas ( 12 ) which comprises at least carbon, whereby the deposited carbon material ( 17 ) forms the Schottky contact ( 16 ) on the semiconductor ( 14 ).

公开(公告)号：DE102004001340A1

公开(公告)日：2005-08-04

申请号：DE102004001340

申请日：2004-01-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDEL ROBERT ,  KREUPL FRANZ

IPC: B82B3/00 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40

Abstract: A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure.