公开(公告)号：WO03050868A3

公开(公告)日：2003-09-04

申请号：PCT/DE0203998

申请日：2002-10-23

Applicant: INFINEON TECHNOLOGIES AG ,  KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

Inventor： KREUPL FRANZ ,  HOENLEIN WOLFGANG ,  STEINHOEGL WERNER

IPC: H01L21/768 ,  H01L51/30 ,  C01B31/02 ,  H01L23/522

CPC classification number: H01L21/7682 ,  B82Y10/00 ,  H01L51/0048 ,  H01L2221/1047 ,  Y10S977/742

Abstract: The invention relates to a method for producing a layered assembly and to a layered assembly (200). According to said method, two substantially parallel electrically conductive strip conductors (202, 203) are configured on a substrate and at least one auxiliary structure (205a, 205b, 205c) is configured on said substrate (201) between the two strip conductors (202, 203), running in a first direction (206), said first direction (206) forming an acute angle of at least 45 DEG or a right angle with a connecting axis of the strip conductors that runs at right angles to both strip conductors (202, 203). The invention is characterised in that the auxiliary structure or structures (205a, 205b, 205c) is or are produced from one material and said structure or structures can be selectively removed from the dielectric layer (204). In addition, a dielectric layer (204) is configured between the two strip conductors in such a way that the auxiliary structure or structures (205a, 205b, 205c) is or are at least partially covered by the dielectric layer (204).

Abstract translation: 本发明涉及一种用于制造层结构的方法，和层布置。 在用于制造层结构（200），两个基本上相互平行的导电迹线（202,203）的方法形成在衬底上的衬底，至少一个辅助结构（205A，205B，205C）上（201） 且沿第一方向延伸的两个导体（202，203）之间（206）形成，该第一方向（206）与垂直于延伸的互连的连接轴线的锐角或直角两个互连（202，203）至少 包括45°的角度，其中，所述至少一个辅助结构（205A，205B，205C）由介电层（204）的至少一个辅助结构是可选择性去除的材料制成。 此外，在两个导体轨道之间形成的介电层（204），使得从电介质层（204）的所述至少一个辅助结构（205A，205B，205C）至少部分地被覆盖。

公开(公告)号：WO2004040668A3

公开(公告)日：2004-07-08

申请号：PCT/DE0303612

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.

Abstract translation: 本发明涉及一种场效应晶体管装置和一种电路阵列。 场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。 此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。 纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

公开(公告)号：WO0250842A3

公开(公告)日：2002-12-27

申请号：PCT/DE0104785

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL HOLGER ,  HOENIGSCHMID HEINZ ,  HOENLEIN WOLFGANG ,  HANEDER THOMAS ,  ULLMANN MARC

Inventor： GOEBEL HOLGER ,  HOENIGSCHMID HEINZ ,  HOENLEIN WOLFGANG ,  HANEDER THOMAS ,  ULLMANN MARC

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22 ,  Y10S977/943

Abstract: The status is read out from or stored in the ferroelectrical transistor. During the reading out or storing of the status, at least one further ferroelectrical transistor in the memory matrix is controlled such as to be operated in the depletion region thereof.

Abstract translation: 该状态从铁电晶体管读出或存储在铁电晶体管中。 在读取或存储状态期间，存储器矩阵中的至少一个另外的铁电晶体管被驱动，使得其在其耗尽区中操作。

公开(公告)号：WO2004040644A3

公开(公告)日：2004-08-12

申请号：PCT/DE0303589

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8239 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/16 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L51/057

Abstract: The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

Abstract translation: 本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。 该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

公开(公告)号：WO02099845A3

公开(公告)日：2003-08-21

申请号：PCT/DE0202026

申请日：2002-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  KREUPL FRANZ ,  SIMBUERGER WERNER

Inventor： HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  KREUPL FRANZ ,  SIMBUERGER WERNER

IPC: H01L25/18 ,  H01L21/60 ,  H01L23/485 ,  H01L25/065 ,  H01L25/07 ,  H01L23/498 ,  C01B31/02 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01L25/0657 ,  B82Y10/00 ,  B82Y30/00 ,  G01R31/2884 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13193 ,  H01L2224/16145 ,  H01L2224/81065 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: A plurality of nanotubes is mounted on at least one external metallic chip contact of the electronic chip for contacting said electronic chip with an additional electronic chip.

Abstract translation: 在电子芯片中的至少一个外部片金属接触多个纳米管被应用于电子芯片与另外的电子芯片接触。

公开(公告)号：DE102006007331A1

公开(公告)日：2007-08-23

申请号：DE102006007331

申请日：2006-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  UNGER EUGEN ,  HOENLEIN WOLFGANG

IPC: H01L27/08 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: The arrangement has a metallization layer arranged over a substrate, where the metallization layer exhibits strip conductors for connecting electronic components. An electrically conductive layer is arranged over the metallization layer, where a dielectric layer (6) is arranged on or over the electrically conductive layer. Another electrically conductive layer is arranged on or over the dielectric layer, where a protection and insulation layer (8) is arranged on or over the latter electrically conductive layer. A third electrically conductive layer is arranged on or over the insulation layer. An independent claim is also included for a method for manufacturing a multilayer capacitance arrangement.

公开(公告)号：DE10250829B4

公开(公告)日：2006-11-02

申请号：DE10250829

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ

IPC: H01L27/115 ,  G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/12 ,  H01L27/28 ,  H01L29/788 ,  H01L29/792 ,  H01L51/00 ,  H01L51/30

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

公开(公告)号：DE59913465D1

公开(公告)日：2006-06-29

申请号：DE59913465

申请日：1999-07-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER PETER ,  REISINGER HANS ,  STENGL REINHARD ,  BACHHOFER HARALD ,  WENDT HERMANN ,  HOENLEIN WOLFGANG

IPC: H01L21/8247 ,  H01L29/786 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

公开(公告)号：DE69838502T2

公开(公告)日：2008-07-24

申请号：DE69838502

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  ADVANCED TECH MATERIALS

Inventor： HINTERMAIER FRANK S ,  DEHM CHRISTINE ,  HOENLEIN WOLFGANG ,  VAN BUSKIRK PETER C ,  ROEDER JEFFREY F ,  HENDRIX BRYAN C ,  BAUM THOMAS H ,  DESROCHERS DEBRA A

IPC: B32B9/00 ,  C23C16/00 ,  C01G35/00 ,  C23C16/40 ,  C23C16/56 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/105

Abstract: A low temperature CVD process using a tris (beta-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

公开(公告)号：DE10152614A1

公开(公告)日：2003-05-15

申请号：DE10152614

申请日：2001-10-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENLEIN WOLFGANG ,  LAUTERBACH CHRISTL ,  PAULUS CHRISTIAN ,  THEWES ROLAND

IPC: A61B5/00 ,  A61B5/08 ,  A61B5/083 ,  A61C5/00 ,  A61F5/08 ,  A61C8/00

Abstract: The implant is permanently arranged in the region of the upper respiratory and/or food tract of a human being or animal. An independent energy supply (3) is provided in the form of a battery, or mechano-electrical or thermo-electrical transducer. A sensor may be provided for detecting a body-specific parameter of the human or animal, or for detecting a parameter of a substance or gas supplied to the body. The integrated circuit may have a memory (7) and a wireless output unit (6). The implant has an integrated circuit device on a semiconductor chip for carrying out functions associated with the implant. Independent claims are also included for the following: (1) a denture; (2) a nose dilator;and (3) a method of implanting an implant.